d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * or http://www.opensolaris.org/os/licensing.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#pragma ident "%Z%%M% %I% %E% SMI" /* common.h */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifndef CHELSIO_COMMON_H
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define CHELSIO_COMMON_H
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DIMOF(x) (sizeof(x)/sizeof(x[0]))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define NMTUS 8
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAX_NPORTS 4
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define TCB_SIZE 128
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwenum {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_7500,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_8000,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_CHT101,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_CHT110,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_CHT210,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_CHT204,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_CHT204V,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_N110,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_N210,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_COUGAR,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_6800,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_BOARD_SIMUL
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwenum {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_TERM_FPGA,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_TERM_T1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_TERM_T2,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_TERM_T3
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwenum {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_CHELSIO_A,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_IXF1010,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_PM3393,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_VSC7321,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_MAC_DUMMY
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwenum {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_PHY_88E1041,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_PHY_88E1111,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_PHY_88X2010,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_PHY_XPAK,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_PHY_MY3126,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw CHBT_PHY_DUMMY
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwenum {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw PAUSE_RX = 1,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw PAUSE_TX = 2,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw PAUSE_AUTONEG = 4
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Revisions of T1 chip */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define TERM_T1A 0
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define TERM_T1B 1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define TERM_T2 3
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct tp_params {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int pm_size;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int cm_size;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int pm_rx_base;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int pm_tx_base;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int pm_rx_pg_size;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int pm_tx_pg_size;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int pm_rx_num_pgs;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int pm_tx_num_pgs;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int use_5tuple_mode;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct sge_params {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int cmdQ_size[2];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int freelQ_size[2];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int large_buf_capacity;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int rx_coalesce_usecs;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int last_rx_coalesce_raw;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int default_rx_coalesce_usecs;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int sample_interval_usecs;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int coalesce_enable;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int polling;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct mc5_params {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int mode; /* selects MC5 width */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int nservers; /* size of server region */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int nroutes; /* size of routing region */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Default MC5 region sizes */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DEFAULT_SERVER_REGION_LEN 256
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DEFAULT_RT_REGION_LEN 1024
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct pci_params {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned short speed;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char width;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char is_pcix;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct adapter_params {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct sge_params sge;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct mc5_params mc5;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct tp_params tp;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct pci_params pci;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw const struct board_info *brd_info;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned short mtus[NMTUS];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int nports; /* # of ethernet ports */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int stats_update_period;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned short chip_revision;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char chip_version;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char is_asic;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct pci_err_cnt {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int master_parity_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int sig_target_abort;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int rcv_target_abort;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int rcv_master_abort;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int sig_sys_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int det_parity_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int pio_parity_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int wf_parity_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int rf_parity_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int cf_parity_err;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct link_config {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int supported; /* link capabilities */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int advertising; /* advertised capabilities */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned short requested_speed; /* speed user has requested */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned short speed; /* actual link speed */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char requested_duplex; /* duplex user has requested */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char duplex; /* actual link duplex */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char requested_fc; /* flow control user has requested */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char fc; /* actual link flow control */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char autoneg; /* autonegotiating? */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define SPEED_INVALID 0xffff
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define DUPLEX_INVALID 0xff
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct mdio_ops;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct gmac;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct gphy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstruct board_info {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char board;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char port_number;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned long caps;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char chip_term;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char chip_mac;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char chip_phy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int clock_core;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int clock_mc3;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int clock_mc4;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int espi_nports;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int clock_cspi;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned int clock_elmer0;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char mdio_mdien;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char mdio_mdiinv;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char mdio_mdc;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned char mdio_phybaseaddr;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct gmac *gmac;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct gphy *gphy;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct mdio_ops *mdio_ops;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw const char *desc;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw};
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#include "osdep.h"
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifndef PCI_VENDOR_ID_CHELSIO
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define PCI_VENDOR_ID_CHELSIO 0x1425
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwextern struct pci_device_id t1_pci_tbl[];
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic inline int t1_is_asic(const adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return adapter->params.is_asic;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic inline int adapter_matches_type(const adapter_t *adapter,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int version, int revision)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return adapter->params.chip_version == version &&
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw adapter->params.chip_revision == revision;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Returns true if an adapter supports VLAN acceleration and TSO */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic inline int vlan_tso_capable(const adapter_t *adapter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return !t1_is_T1B(adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define for_each_port(adapter, iter) \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw for (iter = 0; iter < (adapter)->params.nports; ++iter)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define board_info(adapter) ((adapter)->params.brd_info)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic inline unsigned int core_ticks_per_usec(const adapter_t *adap)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw{
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return board_info(adap)->clock_core / 1000000;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw}
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw int attempts, int delay);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_interrupts_enable(adapter_t *adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_interrupts_disable(adapter_t *adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_interrupts_clear(adapter_t *adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint elmer0_ext_intr_handler(adapter_t *adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_slow_intr_handler(adapter_t *adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwconst struct board_info *t1_get_board_info(unsigned int board_id);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwconst struct board_info *t1_get_board_info_from_ids(unsigned int devid,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw unsigned short ssid);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw struct adapter_params *p);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_init_hw_modules(adapter_t *adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwint t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_free_sw_modules(adapter_t *adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid t1_fatal_err(adapter_t *adapter);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid link_changed(adapter_t *adapter, int port_id);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwvoid init_mtus(unsigned short mtus[]);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif /* CHELSIO_COMMON_H */