/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
*/
#pragma ident "%Z%%M% %I% %E% SMI" /* common.h */
#ifndef CHELSIO_COMMON_H
#define CHELSIO_COMMON_H
#define DIMOF(x) (sizeof(x)/sizeof(x[0]))
enum {
};
enum {
};
enum {
};
enum {
};
enum {
};
/* Revisions of T1 chip */
#define TERM_T1A 0
struct tp_params {
unsigned int pm_size;
unsigned int cm_size;
unsigned int pm_rx_base;
unsigned int pm_tx_base;
unsigned int pm_rx_pg_size;
unsigned int pm_tx_pg_size;
unsigned int pm_rx_num_pgs;
unsigned int pm_tx_num_pgs;
unsigned int use_5tuple_mode;
};
struct sge_params {
unsigned int large_buf_capacity;
unsigned int rx_coalesce_usecs;
unsigned int last_rx_coalesce_raw;
unsigned int default_rx_coalesce_usecs;
unsigned int sample_interval_usecs;
unsigned int coalesce_enable;
unsigned int polling;
};
struct mc5_params {
};
/* Default MC5 region sizes */
struct pci_params {
unsigned short speed;
unsigned char width;
unsigned char is_pcix;
};
struct adapter_params {
unsigned int stats_update_period;
unsigned short chip_revision;
unsigned char chip_version;
unsigned char is_asic;
};
struct pci_err_cnt {
unsigned int master_parity_err;
unsigned int sig_target_abort;
unsigned int rcv_target_abort;
unsigned int rcv_master_abort;
unsigned int sig_sys_err;
unsigned int det_parity_err;
unsigned int pio_parity_err;
unsigned int wf_parity_err;
unsigned int rf_parity_err;
unsigned int cf_parity_err;
};
struct link_config {
};
struct mdio_ops;
struct gmac;
struct gphy;
struct board_info {
unsigned char board;
unsigned char port_number;
unsigned long caps;
unsigned char chip_term;
unsigned char chip_mac;
unsigned char chip_phy;
unsigned int clock_core;
unsigned int clock_mc3;
unsigned int clock_mc4;
unsigned int espi_nports;
unsigned int clock_cspi;
unsigned int clock_elmer0;
unsigned char mdio_mdien;
unsigned char mdio_mdiinv;
unsigned char mdio_mdc;
unsigned char mdio_phybaseaddr;
const char *desc;
};
#include "osdep.h"
#ifndef PCI_VENDOR_ID_CHELSIO
#endif
extern struct pci_device_id t1_pci_tbl[];
{
}
{
}
/* Returns true if an adapter supports VLAN acceleration and TSO */
{
}
{
}
unsigned short ssid);
struct adapter_params *p);
#endif /* CHELSIO_COMMON_H */