#ifndef __devinfo_h__
#define __devinfo_h__
#include "mac_drv_info.h"
/****************************************************************************
* Shared HW configuration *
****************************************************************************/
/* EPIO definition */
struct mac_addr {
};
/* Up to 16 bytes of NULL-terminated string */
#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
/* Whatever MFW found in NVM
(if multiple found, priority order is: NC-SI, UMP, IPMI) */
/* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
(can only be used when an add-in board, not BMC, pulls-down SPIO4) */
/* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
(can only be used when an add-in board, not BMC, pulls-down SPIO4) */
/* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
(can only be used when an add-in board, not BMC, pulls-down SPIO4) */
/* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For
backwards compatibility, value of 0 is disabling this feature.
That means that though 0 is a valid value, it cannot be
configured. */
/* Output low when PERST is asserted */
/* The fan failure mechanism is usually related to the PHY type
since the power consumption of the board is determined by the PHY.
Currently, fan is required for most designs with SFX7101, BCM8727
and BCM8481. If a fan is not required for a board which uses one
of those PHYs, this field should be set to "Disabled". If a fan is
required for a different PHY type, this option should be set to
"Enabled". The fan failure indication is expected on SPIO5 */
/* ASPM Power Management support */
/* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
tl_control_0 (register 0x2800) */
/* Max number of PF MSIX vectors */
#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
/* This field extends the mf mode chosen in nvm cfg #73 (as we ran
out of bits) */
#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
/* Reserved bits: 226-230 */
/* The output pin template BSC_SEL which selects the I2C for this
port in the I2C Mux */
#define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
/* Use the PIN_CFG_XXX defines on top */
#define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
/* TX lane Polarity swap */
/* TX lane Polarity swap */
/* Selects the port layout of the board */
};
/****************************************************************************
* Port HW configuration *
****************************************************************************/
#define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0
#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0
#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
#define PORT_HW_CFG_UPPERMAC_SHIFT 0
/* Default values: 2P-64, 4P-32 */
#define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
/* Controls the TX laser of the SFP+ module */
#define PORT_HW_CFG_TX_LASER_SHIFT 0
/* Controls the fault module LED of the SFP+ */
/* The output pin TX_DIS that controls the TX laser of the SFP+
module. Use the PIN_CFG_XXX defines on top */
#define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
/* The output pin for SFPP_TYPE which turns on the Fault module LED */
/* The input pin MOD_ABS that indicates whether SFP+ module is
present or not. Use the PIN_CFG_XXX defines on top */
/* The output pin PWRDIS_SFP_X which disable the power of the SFP+
module. Use the PIN_CFG_XXX defines on top */
/*
* The input pin which signals module transmit fault. Use the
* PIN_CFG_XXX defines on top
*/
#define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
/* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
top */
/*
* The output pin which powers down the PHY. Use the PIN_CFG_XXX
* defines on top
*/
/* The output pin values BSC_SEL which selects the I2C for this port
in the I2C Mux */
/*
* The input pin I_FAULT which indicate over-current has occurred.
* Use the PIN_CFG_XXX defines on top
*/
#define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
/* pause on host ring */
#define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
/* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
* LOM recommended and tested value is 0xBEB2. Using a different
* value means using a value not tested by BRCM
*/
#define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
/* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
* value is 0x2. LOM recommended and tested value is 0x2. Using a
* different value means using a value not tested by BRCM
*/
#define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
/* 4 times 16 bits for all 4 lanes. In case external PHY is present
(not direct mode), those values will not take effect on the 4 XGXS
lanes. For some external PHYs (such as 8706 and 8726) the values
will be used to configure the external PHY in those cases, not
all 4 values are needed. */
/* For storing FCOE mac on shared memory */
#define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
/* wwpn for npiv enabled */
#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0
/* wwpn for npiv valid addresses */
/* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */
/* number of vfs per PF, if 0 - sriov disabled */
#define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0
/* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
84833 only */
#define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
#define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
/* When KR link is required to be set to force which is not
KR-compliant, this parameter determine what is the trigger for it.
When GPIO is selected, low input will force the speed. Currently
default speed is 1G. In the future, it may be widen to select the
forced speed in with another parameter. Note when force-1G is
enabled, it override option 56: Link Speed option. */
/* Enable to determine with which GPIO to reset the external phy */
/* Enable BAM on KR */
/* Enable Common Mode Sense */
/* Determine the Serdes electrical interface */
/* SFP+ main TAP and post TAP volumes */
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
/* In the case where two media types (e.g. copper and fiber) are
present and electrically active at the same time, PHY Selection
will determine which of the two PHYs will be designated as the
Active PHY and used for a connection to the network. */
#define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
/* When enabled, all second phy nvram parameters will be swapped
with the first phy parameters */
/* Address of the second external phy */
#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
/* The second XGXS external PHY type */
/* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
8706, 8726 and 8727) not all 4 values are needed. */
#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
/* AN and forced */
/* forced only */
/* forced only */
/* forced only */
#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
/* Indicate whether to swap the external phy polarity */
#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
/* A place to hold the original MAC address as a backup */
};
/****************************************************************************
* Shared Feature configuration *
****************************************************************************/
/* Use NVRAM values instead of HW default values */
0x00000002
0x00000000
0x00000002
/* Override the OTP back to single function mode. When using GPIO,
high means only SF, 0 is according to CLP configuration */
/* Act as if the FCoE license is invalid */
/* Force FLR capability to all ports */
/* Act as if the iSCSI license is invalid */
/* The interval in seconds between sending LLDP packets. Set to zero
to disable the feature */
/* The assigned device type ID for LLDP usage */
};
/****************************************************************************
* Port Feature configuration *
****************************************************************************/
#define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0
/* Advertise expansion ROM even if MBA is disabled */
/* Check the optic vendor via i2c against a list of approved modules
in a separate nvram image */
0x00000000
0x20000000
/* Default is used when driver sets to "auto" mode */
#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
#define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
/* (forced) low speed switch (< 10G) */
/* (forced) high speed switch (>= 10G) */
/* The default for MCP link configuration,
uses the same defines as link_config */
/* The default for the driver of the second external phy,
uses the same defines as link_config */
/* The default for MCP of the second external phy,
uses the same defines as link_config */
/* EEE power saving mode */
#define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
};
/****************************************************************************
* Device Information *
****************************************************************************/
};
/* Threshold in celcius to start using the fan */
/* Threshold in celcius to shut down the board */
/* EPIO of fan temperature status */
/* EPIO of shut down temperature status */
/* EPIO of shut down temperature status */
/* MFW flavor to be used */
/* Should NIC data query remain enabled upon last drv unload */
/* Switching regulator loop gain */
/* whether shadow swim feature is supported */
/* Overide PCIE revision ID when enabled the,
revision ID will set to B1=='0x11' */
/* Bypass slicer offset tuning */
/* Control Revision ID */
/* Threshold in celcius for max continuous operation */
/* Threshold in celcius for sensor caution */
/* wwn node prefix to be used (unless value is 0) */
/* wwn port prefix to be used (unless value is 0) */
/* wwn port prefix to be used (unless value is 0) */
/* General debug nvm cfg */
#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0
/* Debug signet rx threshold */
/* Enable IFFE feature */
/* Allowable port enablement (bitmask for ports 3-1) */
/* Allow iSCSI offload override */
/* Allow FCoE offload override */
/* Tie to adaptor */
/* Currently enabled port(s) (bitmask for ports 3-1) */
/* Current iSCSI offload */
/* Current FCoE offload */
/* FW set this pin to "0" (assert) these signal if either of its MAC
* or PHY specific threshold values is exceeded.
*/
/* MAC die temperature threshold in Celsius. */
/* PHY die temperature threshold in Celsius. */
/* External pins to communicate with host.
*/
};
#endif