/*****************************************************************************
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*
* Copyright 2014 QLogic Corporation
* The contents of this file are subject to the terms of the
* QLogic End User License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*
*****************************************************************************/
#if defined(USER_LINUX)
typedef int mm_spin_lock_t;
#else
#include "ediag_compat.h"
// portable integer type of the pointer size for current platform (64/32)
typedef unsigned long mm_int_ptr_t;
#define mm_read_barrier_imp() \
do { \
barrier(); \
ediag_rmb(); \
} while(0)
#define mm_write_barrier_imp() \
do { \
barrier(); \
ediag_wmb(); \
} while(0)
#define mm_barrier_imp() \
do { \
barrier(); \
ediag_rmb(); \
ediag_wmb(); \
} while(0)
/* returns the decremented value */
#define mm_atomic_cmpxchg_imp(_p, _cmp, _new_v) ediag_atomic_cmpxchg((s32_t *)_p, (int)_cmp, (int)_new_v)
#define mm_atomic_and_imp(p, v) \
do { \
*(p) = *(p) & (v); \
} while (0)
#define mm_atomic_or_imp(p, v) \
do { \
*(p) = *(p) | (v); \
} while (0)
LM_BAR_WR32_ADDRESS((PDEV), ((u8_t *)PFDEV(PDEV)->context_info->array[VF_TO_PF_CID((PDEV),(CID))].cid_resc.mapped_cid_bar_addr + (DPM_TRIGER_TYPE)), (VAL))
void MM_ACQUIRE_LOADER_LOCK_IMP(void);
void MM_RELEASE_LOADER_LOCK_IMP(void);
#ifdef VF_INVOLVED
#endif /* VF_INVOLVED */
struct _lm_device_t * pdev,
);
void mm_bar_read_byte(
struct _lm_device_t * _pdev,
);
void mm_bar_read_word(
struct _lm_device_t * _pdev,
);
void mm_bar_read_dword(
struct _lm_device_t * _pdev,
);
void mm_bar_read_ddword(
struct _lm_device_t * _pdev,
);
void mm_bar_write_byte(
struct _lm_device_t * _pdev,
);
void mm_bar_write_word(
struct _lm_device_t * _pdev,
);
void mm_bar_write_dword(
struct _lm_device_t * _pdev,
);
void mm_io_write_dword(
struct _lm_device_t * _pdev,
void * addr,
);
void mm_bar_write_ddword(
struct _lm_device_t * _pdev,
);
void mm_bar_copy_buffer(
struct _lm_device_t * _pdev,
);
{
return ediag_le16_to_cpu(val);
}
{
return ediag_le32_to_cpu(val);
}
{
return ediag_be32_to_cpu(val);
}
{
return ediag_be16_to_cpu(val);
}
{
return ediag_cpu_to_be32(val);
}
{
return ediag_cpu_to_be16(val);
}
{
return ediag_cpu_to_le16(val);
}
{
return ediag_cpu_to_le32(val);
}
u64_t mm_query_system_time(void);
/* the following are __LINUX only... */
struct common_ramrod_eth_rx_cqe *cqe);
struct event_ring_msg *msg);
#endif