/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 2010-2013, by Broadcom, Inc.
* All Rights Reserved.
*/
/*
* All rights reserved.
*/
#ifndef _BGE_HW_H
#define _BGE_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* First section:
* Identification of the various Broadcom chips
*
* Note: the various ID values are *not* all unique ;-(
*
* Note: the presence of an ID here does *not* imply that the chip is
* supported. At this time, only the 5703C, 5704C, and 5704S devices
* used on the motherboards of certain Sun products are supported.
*
* Note: the revision-id values in the PCI revision ID register are
* *NOT* guaranteed correct. Use the chip ID from the MHCR instead.
*/
/*
* Second section:
* Offsets of important registers & definitions for bits therein
*/
/*
* PCI-X registers & bits
*/
/*
* Miscellaneous Host Control Register, in PCI config space
*/
/* (0xf << 28) touches all 5717 and 5725 series as well (OK) */
/*
*
* Note that several fields previously defined here have been deleted
* as they are not implemented in the 5703/4.
*
* Note: the value of this register is critical. It is possible to
* cause various unpleasant effects (DTOs, transaction deadlock, etc)
* by programming the wrong value. The value #defined below has been
* tested and shown to avoid all known problems. If it is to be changed,
* correct operation must be reverified on all supported platforms.
*
* In particular, we set both watermark fields to 2xCacheLineSize (128)
* bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions
* with Tomatillo's internal pipelines, that otherwise result in stalls,
* repeated retries, and DTOs.
*/
/*
* These are the actual values to be put into the fields shown above
*/
/*
* PCI State Register, in PCI config space
*
* Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit
* is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW
*/
/*
* PCI Clock Control Register, in PCI config space
*/
/*
* Dual MAC Control Register, in PCI config space
*/
/*
* Register Indirect Access Address Register, 0x78 in PCI config
* space. Once this is set, accesses to the Register Indirect
* Access Data Register (0x80) refer to the register whose address
* is given by *this* register. This allows access to all the
* operating registers, while using only config space accesses.
*
* Note that the address written to the RIIAR should lie in one
* of the following ranges:
* 0x00000000 <= address < 0x00008000 (regular registers)
* 0x00030000 <= address < 0x00034000 (RxRISC scratchpad)
* 0x00034000 <= address < 0x00038000 (TxRISC scratchpad)
* 0x00038000 <= address < 0x00038800 (RxRISC ROM)
*/
/*
* Memory Window Base Address Register, 0x7c in PCI config space
* Once this is set, accesses to the Memory Window Data Access Register
* (0x84) refer to the word of NIC-local memory whose address is given
* by this register. When used in this way, the whole of the address
* written to this register is significant.
*
* This register also provides the 32K-aligned base address for a 32K
* region of NIC-local memory that the host can directly address in
* the upper 32K of the 64K of PCI memory space allocated to the chip.
* In this case, the bottom 15 bits of the register are ignored.
*
* Note that the address written to the MWBAR should lie in the range
* 0x00000000 <= address < 0x00020000. The rest of the range up to 1M
* (i.e. 0x00200000 <= address < 0x01000000) would be valid if external
* memory were present, but it's only supported on the 5700, not the
* 5701/5703/5704.
*/
/*
* The PCI express device control register and device status register
* which are only applicable on BCM5751 and BCM5721.
*/
/*
* Where to find things in NIC-local (on-chip) memory
*/
/*
* Note: the (non-bogus) values below are appropriate for systems
* without external memory. They would be different on a 5700 with
* external memory.
*
* Note: The higher send ring addresses and the mini ring shadow
* buffer address are dummies - systems without external memory
* are limited to 4 send rings and no mini receive ring.
*/
/*
* Put this in the GENCOMM port to tell the firmware not to run PXE
*/
/*
* The remaining registers appear in the low 32K of regular
* PCI Memory Address Space
*/
/*
* All the state machine control registers below have at least a
* <RESET> bit and an <ENABLE> bit as defined below. Some also
* have an <ATTN_ENABLE> bit.
*/
/*
* Other bits in some of the above state machine control registers
*/
/*
* Transmit MAC Mode Register
* (TRANSMIT_MAC_MODE_REG, 0x045c)
*/
/*
* Receive MAC Mode Register
* (RECEIVE_MAC_MODE_REG, 0x0468)
*/
/*
* Receive BD Initiator Mode Register
* (RCV_BD_INITIATOR_MODE_REG, 0x2c00)
*
* Each of these bits controls whether ATTN is asserted
* on a particular condition
*/
/*
* Receive Data & Receive BD Initiator Mode Register
* (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400)
*
* Each of these bits controls whether ATTN is asserted
* on a particular condition
*/
/*
* Host Coalescing Mode Control Register
* (HOST_COALESCE_MODE_REG, 0x3c00)
*/
/*
* Memory Arbiter Mode Register
* (MEMORY_ARBITER_MODE_REG, 0x4000)
*/
/*
* Buffer Manager Mode Register
* (BUFFER_MANAGER_MODE_REG, 0x4400)
*
* In addition to the usual error-attn common to most state machines
* this register has a separate bit for attn on running-low-on-mbufs
*/
/*
* Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
* 0x4800 and WRITE_DMA_MODE_REG, 0x4c00)
*
* These registers each contain a 2-bit priority field, which controls
* the relative priority of that type of DMA (read vs. write vs. MSI),
* and a set of bits that control whether ATTN is asserted on each
* particular condition
*/
/*
* BCM5755, 5755M, 5906, 5906M only
* 1 - Enable Fix. Device will send out the status block before
* the interrupt message
* 0 - Disable fix. Device will send out the interrupt message
* before the status block
*/
/*
* End of state machine control register definitions
*/
/*
* High priority mailbox registers.
* Mailbox Registers (8 bytes each, but high half unused)
*/
/*
* Low priority mailbox registers, for BCM5906, BCM5906M.
*/
/*
*/
/*
* Ethernet MAC Mode Register
*/
/*
* Ethernet MAC Status & Event Registers
*/
/*
* Ethernet MAC LED Control Register
*
* NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and
* the external LED driver circuitry is wired up to assume that this mode
* will always be selected. Software must not change it!
*/
/*
* MAC Address registers
*
* These four eight-byte registers each hold one unicast address
* (six bytes), right justified & zero-filled on the left.
* They will normally all be set to the same value, as a station
* usually only has one h/w address. The value in register 0 is
* used for pause packets; any of the four can be specified for
* substitution into other transmitted packets if required.
*/
/*
* More MAC Registers ...
*/
/*
* MII access registers
*/
#define MI_COMMS_DATA_SHIFT 0
/*
* These four-byte registers constitute a hash table for deciding
* whether to accept incoming multicast packets. The bits are
* numbered in big-endian fashion, from hash 0 => the MSB of
* register 0 to hash 127 => the LSB of the highest-numbered
* register.
*
* NOTE: the 5704 can use a 256-bit table (registers 0-7) if
* enabled by setting the appropriate bit in the Rx MAC mode
* register. Otherwise, and on all earlier chips, the table
* is only 128 bits (registers 0-3).
*/
#define MAC_HASH_4_REG 0x????
#define MAC_HASH_5_REG 0x????
#define MAC_HASH_6_REG 0x????
#define MAC_HASH_7_REG 0x????
/*
*/
/*
* Receive Rules definition
*/
/*
* 1000BaseX low-level access registers
*/
/*
* Autoneg code bits for the 1000BASE-X AUTONEG registers
*/
/*
* SerDes Registers (5703S/5704S only)
*/
/* 5780/5714 only */
/*
* SGMII Status Register (5717/18/19/20 only)
*/
/*
* Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only)
*/
/*
* Send Data Initiator Registers
*/
/*
* Send Buffer Descriptor Selector Control Registers
*/
/*
* Receive List Placement Registers
*/
/*
* Receive Data & BD Initiator Registers
*/
/*
* Receive Buffer Descriptor Ring Control Block Registers
* NB: sixteen bytes (128 bits) each
*/
/*
* Receive Buffer Descriptor Ring Replenish Threshold Registers
*/
/*
* CPMU registers (5717/18/19/20 only)
*/
/*
* EEE registers (5718/19/20 only)
*/
/* Clause 45 expansion registers */
/*
* Host Coalescing Engine Control Registers
*/
/*
* Mbuf Pool Initialisation & Watermark Registers
*
* There are some conflicts in the PRM; compare the recommendations
* on pp. 115, 236, and 339. The values here were recommended by
* dkim@broadcom.com (and the PRM should be corrected soon ;-)
*/
/*
* DMA Descriptor Pool Initialisation & Watermark Registers
*/
/*
*/
/*
*/
/*
*/
/*
* V? RISC Registerss
*/
/*
* Miscellaneous Configuration Register
*
* This contains various bits relating to power control (which differ
* among different members of the chip family), but the important bits
* for our purposes are the RESET bit and the Timer Prescaler field.
*
* The RESET bit in this register serves to reset the whole chip, even
* including the PCI interface(!) Once it's set, the chip will not
* respond to ANY accesses -- not even CONFIG space -- until the reset
* completes internally. According to the PRM, this should take less
* than 100us. Any access during this period will get a bus error.
*
* The Timer Prescaler field must be programmed so that the timer period
* is as near as possible to 1us. The value in this field should be
* the Core Clock frequency in MHz minus 1. From my reading of the PRM,
* the Core Clock should always be 66MHz (independently of the bus speed,
* at least for PCI rather than PCI-X), so this register must be set to
* the value 0x82 ((66-1) << 1).
*/
/*
* Miscellaneous Local Control Register (MLCR)
*/
/*
* This value defines all GPIO bits as INPUTS, but sets their default
* values as outputs to HIGH, on the assumption that external circuits
* (if any) will probably be active-LOW with passive pullups.
*
* The Claymore blade uses GPIO1 to control writing to the SEEPROM in
* just this fashion. It has to be set as an OUTPUT and driven LOW to
* enable writing. Otherwise, the SEEPROM is protected.
*/
/*
*/
/*
* "Linearised" address mask, treating multiple devices as consecutive
*/
/*
* Non-Volatile Memory Interface Registers
* Note: on chips that support the flash interface (5702+), flash is the
* default and the legacy seeprom interface must be explicitly enabled
* if required. On older chips (5700/01), SEEPROM is the default (and
* only) non-volatile memory available, and these registers don't exist!
*/
/*
* NVM access register
* Applicable to BCM5721,BCM5751,BCM5752,BCM5714
* and BCM5715 only.
*/
/*
* TLP Control Register
* Applicable to BCM5721 and BCM5751 only
*/
/*
* PHY Test Control Register
* Applicable to BCM5721 and BCM5751 only
*/
/*
* The internal firmware expects a certain layout of the non-volatile
* memory (if fitted), and will check for it during startup, and use the
* contents to initialise various internal parameters if it looks good.
*
* The offsets and field definitions below refer to where to find some
* important values, and how to interpret them ...
*/
/*
* Vendor-specific MII registers
*/
/*
* Bits in the MII_EXT_CONTROL register
*/
/*
* Bits in the MII_EXT_STATUS register
*/
/*
* The AUX CONTROL register is seriously weird!
*
* It hides (up to) eight 'shadow' registers. When writing, which one
* of them is written is determined by the low-order bits of the data
* written(!), but when reading, which one is read is determined by the
* value previously written to (part of) one of the shadow registers!!!
*/
/*
* Shadow register numbers
*/
#define MII_AUX_CTRL_NORMAL 0
/*
* Selected bits in some of the shadow registers ...
*/
/*
* Write this value to the AUX control register
* to select which shadow register will be read
*/
/*
* Bits in the MII_AUX_STATUS register
*/
/*
* Bits in the MII_INTR_STATUS and MII_INTR_MASK registers
*/
/*
* Third section:
* Hardware-defined data structures
*
* Note that the chip is naturally BIG-endian, so, for a big-endian
* host, the structures defined below match those described in the PRM.
* For little-endian hosts, some structures have to be swapped around.
*/
#if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN)
#endif
/*
* Architectural constants: absolute maximum numbers of each type of ring
*/
#ifdef BGE_EXT_MEM
#else
#endif
/* only with ext mem) */
/*
* Hardware-defined Ring Control Block
*/
typedef struct {
#ifdef _BIG_ENDIAN
#else
#endif /* _BIG_ENDIAN */
} bge_rcb_t;
/*
* Hardware-defined Send Buffer Descriptor
*/
typedef struct {
#ifdef _BIG_ENDIAN
#else
#endif /* _BIG_ENDIAN */
} bge_sbd_t;
/*
* Hardware-defined Receive Buffer Descriptor
*/
typedef struct {
#ifdef _BIG_ENDIAN
#else
#endif /* _BIG_ENDIAN */
} bge_rbd_t;
/*
* Hardware-defined Status Block,Size of status block
* is actually 0x50 bytes.Use 0x80 bytes for cache line
* alignment.For BCM5705/5788/5721/5751/5752/5714
* and 5715,there is only 1 recv and send ring index,but
* driver defined 16 indexs here,please pay attention only
* one ring is enabled in these chipsets.
*/
typedef struct {
struct {
#ifdef _BIG_ENDIAN
#else
#endif /* _BIG_ENDIAN */
} bge_status_t;
/*
* Hardware-defined Receive BD Rule
*/
typedef struct {
/*
* This describes which sub-rule slots are used by a particular rule.
*/
typedef struct {
int start;
int count;
/*
* Indexes into the <buff_cons_index> array
*/
#ifdef _BIG_ENDIAN
#define STATUS_STD_BUFF_CONS_INDEX 0
#else
#define STATUS_MINI_BUFF_CONS_INDEX 0
#endif /* _BIG_ENDIAN */
/*
* Bits in the <flags_n_tag> word
*/
/*
* The tag from the status block is fed back to Interrupt Mailbox 0
* (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This
* lets the chip know what updates have been processed, so it can
* reassert its interrupt if more updates have occurred since.
*
* These macros extract the tag from the <flags_n_tag> word, shift
* it to the proper position in the Mailbox register, and provide
* the complete values to write to INTERRUPT_MBOX_0_REG to disable
* or enable interrupts
*/
/*
* Hardware-defined Statistics Block Offsets
*
* These are given in the manual as addresses in NIC memory, starting
* from the NIC statistics area base address of 0x300; but here we
* convert them into indexes into an array of (uint64_t)s, so we can
* use them directly for accessing the copy of the statistics block
* that the chip DMAs into main memory ...
*/
typedef enum {
/*
* Hardware-defined Statistics Block
*
* Another view of the statistic block, as a array and a structure ...
*/
typedef union {
struct {
} s;
typedef struct {
#ifdef BGE_IPMI_ASF
/*
* Device internal memory entries
*/
/*
* RX-RISC event register
*/
#endif /* BGE_IPMI_ASF */
/* APE registers. Accessible through BAR1 */
/* APE shared memory. Accessible through BAR1 */
#define APE_HOST_HEARTBEAT_INT_DISABLE 0
/* APE convenience enumerations. */
#define BGE_APE_LOCK_PHY0 0
#ifdef __cplusplus
}
#endif
#endif /* _BGE_HW_H */