audiols.h revision 48722b5f422aa5e059f333d8c7384ffd184fe739
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Purpose: Definitions for the Creative Audigy LS driver
*/
/*
* This file is part of Open Sound System
*
* Copyright (C) 4Front Technologies 1996-2009.
*
* This software is released under CDDL 1.0 source license.
* See the COPYING file included in the main directory of this source
* distribution for the license terms and conditions.
*/
#ifndef AUDIGYLS_H
#define AUDIGYLS_H
#define AUDIGYLS_NAME "audiols"
#define AUDIGYLS_NUM_PORT 2
#define AUDIGYLS_PLAY_PORT 0
#define AUDIGYLS_REC_PORT 1
/*
* Number of fragments must be multiple of 2 because the
* hardware supports only full and half buffer interrupts. In
* addition it looks like 8 fragments is the minimum.
*/
#define PCI_VENDOR_ID_CREATIVE 0x1102
#define PCI_DEVICE_ID_CREATIVE_AUDIGYLS 0x0007
#define AUDIGYLS_MAX_INTRS 256
#define AUDIGYLS_MIN_INTRS 24
#define AUDIGYLS_INTRS 100
/*
* PCI registers
*/
#define PR 0x00
#define DR 0x04
#define IPR 0x08
#define IER 0x0C
#define INTR_PCI (1 << 0)
#define HC 0x14
#define GPIO 0x18
#define AC97D 0x1C
#define AC97A 0x1E
/*
* Indirect registers
*/
#define SCS3 0x041
#define SCS0 0x042
#define SCS1 0x043
#define SCS2 0x044
/* MIDI UART */
/*
* Audio interrupt bits
*/
#define SA_48K 0
#define SA_44K 1
#define SA_96K 2
#define SA_192K 3
#define RECSEL_SPDIFOUT 0
#define RECSEL_I2SOUT 1
#define RECSEL_SPDIFIN 2
#define RECSEL_I2SIN 3
#define RECSEL_AC97 4
#define RECSEL_SRC 5
typedef struct _audigyls_dev_t audigyls_dev_t;
typedef struct _audigyls_port_t audigyls_port_t;
typedef enum {
CTL_FRONT = 0,
CTL_NUM /* must be last */
typedef struct audigyls_ctrl
{
struct _audigyls_port_t
{
int direction;
int started;
unsigned fragfr;
unsigned fragsz;
unsigned nchan;
int syncdir;
};
struct _audigyls_dev_t
{
unsigned intrs;
unsigned timer;
int nactive; /* Num active ports */
char digital_enable; /* Orange combo-jack mode */
};
#endif /* AUDIGYLS_H */