/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Purpose: Definitions for the Creative Audigy LS driver
*/
/*
* This file is part of Open Sound System
*
* Copyright (C) 4Front Technologies 1996-2009.
*
* This software is released under CDDL 1.0 source license.
* See the COPYING file included in the main directory of this source
* distribution for the license terms and conditions.
*/
/*
* PCI registers
*/
#
define INTR_TXA (
1 <<
1)
/* midi-a tx */#
define INTR_RXA (
1 <<
2)
/* midi-a rx */#
define INTR_IT2 (
1 <<
3)
/* timer 2, 44.1 kHz */#
define INTR_IT1 (
1 <<
4)
/* timer 1, 192 kHz */#
define INTR_SS_ (
1 <<
5)
/* spdif status */#
define INTR_SRT (
1 <<
6)
/* sample rate status */#
define INTR_AI (
1 <<
8)
/* audio pending interrupt */#
define INTR_TXB (
1 <<
16)
/* midi-b tx */#
define INTR_RXB (
1 <<
17)
/* midi-b rx */
#
define HC_PF (
1 <<
11)
/* play fmt 1 = 32b, 0 = 16b */#
define HC_RF (
1 <<
10)
/* rec fmt 1 = 32b, 0 = 16b */#
define HC_AEN (
1 << 0)
/* audio enable */
/*
* Indirect registers
*/
#
define PTBA 0x000 /* gather play table base address */#
define PTBS 0x001 /* gather play table buffer size */#
define PTCA 0x002 /* gather play table current addr ptr */#
define PFBA 0x004 /* play fifo base address */#
define PFBS 0x005 /* play fifo buffer size */#
define CPFA 0x006 /* current play fifo address */#
define PFEA 0x007 /* play fifo end address */#
define RFBA 0x010 /* record fifo base address */#
define RFBS 0x011 /* record fifo buffer size */#
define CRFA 0x012 /* current record fifo address */#
define CDL 0x020 /* play fifo cache data, 0x20-0x2f */#
define SA 0x040 /* start audio */#
define SPC 0x045 /* spdif output control */#
define WMARK 0x046 /* test purposes only */#
define SPSC 0x049 /* spdif input control */#
define RCD 0x050 /* record cache data, 0x50-0x5f */#
define P17RECSEL 0x060 /* record fifo map address */#
define P17RECVOLL 0x061 /* record fifo volume control (lo) */#
define P17RECVOLH 0x062 /* record fifo volume control (hi) */
#
define MIXVOL_SPDIF 0x066 /* spdif mixer input volume control */#
define MIXVOL_I2S 0x06a /* i2s mixer input volume control */
/* MIDI UART */
#
define MUDATA 0x06c /* midi uart a data */#
define MUDATB 0x06e /* midi uart b data */
#
define SRT 0x070 /* sample rate tracker status */#
define SRCTL 0x071 /* sample rate control */#
define AUDCTL 0x072 /* audio output control */#
define CHIP_ID 0x074 /* chip id */#
define AIE 0x075 /* audio interrupt enable */#
define AIP 0x076 /* audio interrupt */#
define WALL192 0x077 /* wall clock @ 192 kHz */#
define WALL441 0x078 /* wall clock @ 44.1 kHz */#
define IT 0x079 /* interval timer */#
define SPI 0x07a /* spi interface */#
define I2C_A 0x07b /* i2c address */#
define I2C_0 0x07c /* i2c data */#
define I2C_1 0x07d /* i2c data */
/*
* Audio interrupt bits
*/
#
define AI_PFH 0x00000001 /* playback fifo half loop */#
define AI_PFF 0x00000010 /* playback fifo loop */#
define AI_TFH 0x00000100 /* playback table half loop */#
define AI_TFF 0x00001000 /* playback table loop */#
define AI_RFH 0x00010000 /* capture table half loop */#
define AI_RFF 0x00100000 /* capture fifo loop */#
define AI_EAI 0x01000000 /* enables audio end interrupt */
typedef enum {
{
{
};
{
int nactive;
/* Num active ports */
};
#endif /* AUDIGYLS_H */