/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARN_REG_H
#define _ARN_REG_H
#ifdef __cplusplus
extern "C" {
#endif
#define AR_TIMT_LAST_S 0
#define AR_RIMT_LAST_S 0
#define AR_TXCFG_DMASZ_4B 0
#define AR_RXCFG_DMASZ_4B 0
#define AR_MACMISC_DMA_OBS_LINE_0 0
#define AR_ISR_S0_QCU_TXOK_S 0
#define AR_ISR_S1_QCU_TXERR_S 0
#define AR_IMR_S0_QCU_TXOK_S 0
#define AR_IMR_S1_QCU_TXERR_S 0
#define AR_IMR_S2_QCU_TXURN_S 0
#define AR_ISR_S0_QCU_TXOK_S 0
#define AR_ISR_S1_QCU_TXERR_S 0
#define AR_Q_CBRCFG_INTERVAL_S 0
#define AR_Q_RDYTIMECFG_DURATION_S 0
#define AR_Q_MISC_FSP_ASAP 0
#define AR_D_LCL_IFS_CWMIN_S 0
#define AR_D_RETRY_LIMIT_FR_SH_S 0
#define AR_D_CHNTIME_DUR_S 0
#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0
#define AR_D_TXBLK_WRITE_BITMASK_S 0
#define AR_D_FPCTL_DCU_S 0
#define AR_CFG_SCLK_RATE_IND_S 0
#define AR_HOST_TIMEOUT_APB_CNTR_S 0
#define AR_SREV \
#define AR_SREV_ID \
#define AR_SREV_REVISION_5416_10 0
#define AR_SREV_REVISION_9160_10 0
#define AR_SREV_REVISION_9280_10 0
#define AR_SREV_REVISION_9285_10 0
enum {
/* AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, */
};
#define AR_GPIO_INTR_POL_VAL_S 0
#define AR_GPIO_INPUT_MUX2_CLK25_S 0
#define AR_EEPROM_STATUS_DATA_VAL_S 0
#define AR_RTC_9160_PLL_DIV_S 0
#define AR_RTC_RC \
#define AR_RTC_PLL_CONTROL \
#define AR_RTC_PLL_DIV_S 0
#define AR_RTC_RESET \
#define AR_RTC_STATUS \
#define AR_RTC_STATUS_M \
#define AR_RTC_SLEEP_CLK \
#define AR_RTC_FORCE_WAKE \
#define AR_RTC_INTR_CAUSE \
#define AR_RTC_INTR_ENABLE \
#define AR_RTC_INTR_MASK \
#define AR9285_AN_RF2G3_DB1_2_S 0
#define AR9285_AN_RXTXBB1_SPARE9_S 0
#define AR_TIME_OUT_ACK_S 0
#define AR_QUIET1_NEXT_QUIET_S 0
#define AR_QUIET2_QUIET_PERIOD_S 0
#define AR_QOS_NO_ACK_TWO_BIT_S 0
#ifdef __cplusplus
}
#endif
#endif /* _ARN_REG_H */