/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARN_PHY_H
#define _ARN_PHY_H
#ifdef __cplusplus
extern "C" {
#endif
struct ath9k_channel *chan);
struct ath9k_channel *chan);
struct ath9k_channel *chan);
#define AR_PHY_TX_END_DATA_START_S 0
#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
#define AR_PHY_DESIRED_SZ_ADC_S 0
#define AR_PHY_SFCORR_M2COUNT_THR_S 0
#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
#define AR_PHY_RADAR_1_MAXLEN_S 0
#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
#define AR_PHY_EXT_CCA0_THRESH62_S 0
#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
#define AR_PHY_HALFGI_DSC_EXP_S 0
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
/* [12:6] settling time for antenna switch */
#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
#define AR_PHY_FORCE_XPA_CFG_S 0
int r; \
} \
} while (0)
int i; \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* _ARN_PHY_H */