arn_core.h revision e2cf88ac9d753a00c17aa235f6afdc76574fe3a6
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARN_CORE_H
#define _ARN_CORE_H
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/net80211.h>
#include "arn_ath9k.h"
#include "arn_rc.h"
struct ath_node;
/*
* Node type of wifi device
*/
#ifndef DDI_NT_NET_WIFI
#define DDI_NT_NET_WIFI "ddi_network:wifi"
#endif
#define ARN_NODENAME "arn"
#define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0]))
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define ARN_MIN(a, b) ((a) < (b) ? (a) : (b))
#define ARN_MAX(a, b) ((a) > (b) ? (a) : (b))
#define abs(x) ((x) >= 0 ? (x) : -(x))
enum ath9k_key_len {
ATH9K_LEN_WEP40 = 5,
ATH9K_LEN_WEP104 = 13,
};
/*
* Sync a DMA area described by a dma_area_t
*/
#define ARN_LE_READ_16(p) \
((uint16_t) \
#define ARN_LE_READ_32(p) \
((uint32_t) \
<< 32) | \
/* Bit map related macros. */
/* Macro to expand scalars to 64-bit objects */
#define ito64(x) (sizeof (x) == 8) ? \
(((unsigned long long int)(x)) & (0xff)) : \
(sizeof (x) == 16) ? \
(((unsigned long long int)(x)) & 0xffff) : \
((sizeof (x) == 32) ? \
(((unsigned long long int)(x)) & 0xffffffff) : \
(unsigned long long int)(x))
/* increment with wrap-around */
(_l)++; \
} while (0)
/* decrement with wrap-around */
(_l)--; \
} while (0)
#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
// static const uint8_t ath_bcast_mac[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
/* Debugging */
enum ARN_DEBUG {
ARN_DBG_HW = 0x00000001,
ARN_DBG_REG_IO = 0x00000002,
ARN_DBG_QUEUE = 0x00000004,
ARN_DBG_EEPROM = 0x00000008,
ARN_DBG_XMIT = 0x00000010,
ARN_DBG_RECV = 0x00000020,
ARN_DBG_CALIBRATE = 0x00000040,
ARN_DBG_CHANNEL = 0x00000080,
ARN_DBG_INTERRUPT = 0x00000100,
ARN_DBG_REGULATORY = 0x00000200,
ARN_DBG_ANI = 0x00000400,
ARN_DBG_POWER_MGMT = 0x00000800,
ARN_DBG_KEYCACHE = 0x00001000,
ARN_DBG_BEACON = 0x00002000,
ARN_DBG_RATE = 0x00004000,
ARN_DBG_INIT = 0x00008000,
ARN_DBG_ATTACH = 0x00010000,
ARN_DBG_DEATCH = 0x00020000,
ARN_DBG_AGGR = 0x00040000,
ARN_DBG_RESET = 0x00080000,
ARN_DBG_FATAL = 0x00100000,
ARN_DBG_ANY = 0x00200000,
ARN_DBG_ALL = 0x00FFFFFF,
};
/* Debug and log functions */
#ifdef DEBUG
{ command; } \
} while (0)
#else
#endif /* DEBUG */
struct ath_stats {
};
struct dma_area {
/* >= product of above */
};
typedef struct dma_area dma_area_t;
/* Load-time Configuration */
/*
* Per-instance load-time (note: NOT run-time)
* configurations for Atheros Device
*/
struct ath_config {
};
/* Descriptor Management */
#define ATH_TXBUF_RESET(_bf) do { \
sizeof (struct ath_buf_state)); \
} while (0)
enum buffer_type {
};
struct ath_buf_state {
int bfs_nframes; /* # frames in aggregate */
int bfs_seqno; /* sequence number */
int bfs_tidno; /* tid of this frame */
int bfs_retries; /* current retries */
/* key type used to encrypt this frame */
enum ath9k_key_type bfs_keytype;
};
/*
* There is only a single hw descriptor encapsulated here.
*/
struct ath_buf {
/* last buf of this unit (a frame or an aggregate) */
/* we're in list of sc->sc_txbuf_list or asc->asc_rxbuf_list */
};
/*
* reset the rx buffer.
* any new fields added to the athbuf and require
* reset need to be added to this macro.
* currently bf_status is the only one requires that
* requires reset.
*/
/* hw processing complete, desc processed by hal */
#define ATH_BUFSTATUS_DONE 0x00000001
/* hw processing complete, desc hold for hw */
#define ATH_BUFSTATUS_STALE 0x00000002
/* Rx-only: OS is done with this packet and it's ok to queued it to hw */
#define ATH_BUFSTATUS_FREE 0x00000004
/* RX / TX */
#define ATH_MAX_ANTENNA 3
#define ATH_RXBUF 512
#define WME_NUM_TID 16
#define ATH_TXBUF 512
/* max number of transmit attempts (tries) */
#define ATH_TXMAXTRY 13
/* max number of 11n transmit attempts (tries) */
#define ATH_11N_TXMAXTRY 10
/* max number of tries for management and control frames */
#define ATH_MGT_TXMAXTRY 4
#define WME_BA_BMP_SIZE 64
#define WME_MAX_BA WME_BA_BMP_SIZE
/* Wireless Multimedia Extension Defines */
#define WME_AC_BE 0 /* best effort */
#define WME_NUM_AC 4
/*
* Data transmit queue state. One of these exists for each
* hardware transmit queue. Packets sent to us from above
* are assigned to queues based on their priority. Not all
* devices support a complete set of hardware transmit queues.
* For those devices the array sc_ac2q will map multiple
* priorities to fewer hardware queues (typically all to one
* hardware queue).
*/
struct ath_txq {
unsigned long axq_lockflags; /* intr state when must cli */
/* first desc of the last descriptor that contains CTS */
struct ath_desc *axq_lastdsWithCTS;
};
/* per TID aggregate tx state for a destination */
struct ath_atx_tid {
struct ath_atx_ac *ac;
int tidno;
int baw_head; /* first un-acked tx buffer */
int baw_tail; /* next unused tx buffer slot */
int sched;
int paused;
};
/* per access-category aggregate tx state for a destination */
struct ath_atx_ac {
int sched; /* dest-ac is scheduled */
int qnum; /* H/W queue number associated with this AC */
};
/* per dest tx state */
struct ath_atx {
};
/* per-frame tx control block */
struct ath_tx_control {
int if_id;
};
/* per frame tx status block */
struct ath_xmit_status {
/* number of retries to successufully transmit this frame */
int retries;
int flags; /* status of transmit */
#define ATH_TX_ERROR 0x01
#define ATH_TX_XRETRY 0x02
#define ATH_TX_BAR 0x04
};
struct ath_tx_stat {
int rssi; /* RSSI (noise floor ajusted) */
int rateieee; /* data rate xmitted (IEEE rate code) */
int rateKbps; /* data rate xmitted (Kbps) */
int ratecode; /* phy rate code */
int flags; /* validity flags */
/* if any of ctl,extn chain rssis are valid */
#define ATH_TX_CHAIN_RSSI_VALID 0x01
/* if extn chain rssis are valid */
#define ATH_TX_RSSI_EXTN_VALID 0x02
};
struct ath9k_tx_queue_info *qinfo);
void arn_tx_int_proc(void *arg);
/* Node / Aggregation */
#define ADDBA_EXCHANGE_ATTEMPTS 10
/* number of delimiters for encryption padding */
#define ATH_AGGR_ENCRYPTDELIM 10
/* minimum h/w qdepth to be sustained to maximize aggregation */
#define ATH_AGGR_MIN_QDEPTH 2
#define ATH_AMPDU_SUBFRAME_DEFAULT 32
#define IEEE80211_SEQ_SEQ_SHIFT 4
#define IEEE80211_SEQ_MAX 4096
#define IEEE80211_MIN_AMPDU_BUF 0x8
#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
/*
* return whether a bit at index _n in bitmap _bm is set
* _sz is the size of the bitmap
*/
/* return block-ack bitmap index given sequence and starting sequence */
/* returns delimiter padding required given the packet length */
#define ATH_AGGR_GET_NDELIM(_len) \
enum ATH_AGGR_STATUS {
};
struct aggr_rifs_param {
int param_max_frames;
int param_max_len;
int param_rl;
int param_al;
struct ath_rc_series *param_rcs;
};
/* driver-specific node state */
struct ath_node {
#ifdef ARN_11N
struct ath_node_aggr an_aggr;
#endif
};
/*
* Define the scheme that we select MAC address for multiple
* BSS on the same radio. The very first VAP will just use the MAC
* address from the EEPROM. For the next 3 VAPs, we set the
* U/L bit (bit 1) in MAC address, and use the next two bits as the
* index of the VAP.
*/
#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
/* driver-specific vap state */
struct ath_vap {
int av_bslot; /* beacon slot index */
};
/* Beacon Handling */
/*
* Regardless of the number of beacons we stagger, (i.e. regardless of the
* number of BSSIDs) if a given beacon does not go out even after waiting this
* number of beacon intervals, the game's up.
*/
#define ATH_DEFAULT_BMISS_LIMIT 10
/* beacon configuration */
struct ath_beacon_config {
union {
};
void arn_bmiss_proc(void *arg);
/* ANI */
/*
* ANI values for STA only.
* FIXME: Add appropriate values for AP later
*/
struct ath_ani {
unsigned int sc_longcal_timer;
unsigned int sc_shortcal_timer;
unsigned int sc_resetcal_timer;
unsigned int sc_checkani_timer;
};
/* LED Control */
#define ATH_LED_PIN 1
enum ath_led_type {
};
struct ath_led {
enum ath_led_type led_type;
char name[32];
};
/* Rfkill */
/* Main driver core */
/*
* Default cache line size, in bytes.
*/
#define DEFAULT_CACHELINE 32
#define ATH_DEFAULT_NOISE_FLOOR -95
#define ATH_REGCLASSIDS_MAX 10
#define ATH_MAX_SW_RETRIES 10
#define ATH_CHAN_MAX 255
#define IEEE80211_RATE_VAL 0x7f
/*
* The key cache is used for h/w cipher state and also for
* tracking station state such as the current tx antenna.
* We also setup a mapping table between key cache slot indices
* and station state to short-circuit node lookups on rx.
* Different parts have different size key caches. We handle
* up to ATH_KEYMAX entries (could dynamically allocate state).
*/
#define ATH_IF_ID_ANY 0xff
#define ATH_RSSI_DUMMY_MARKER 0x127
#define ATH_RATE_DUMMY_MARKER 0
enum PROT_MODE {
PROT_M_NONE = 0,
};
#define SC_OP_INVALID BIT(0)
struct arn_softc {
struct ath_config sc_config;
/* descriptor structure */
/* pointer to the first "struct ath_buf" */
struct ath_buf *sc_vbufptr;
/* length of all allocated "struct ath_buf" */
int sc_debug;
unsigned int rx_filter;
int sc_slotupdate; /* slot to next advance fsm */
int sc_slottime;
enum PROT_MODE sc_protmode;
enum {
OK, /* no change needed */
UPDATE, /* update pending */
COMMIT /* beacon sent, commit change */
} sc_updateslot; /* slot time update fsm */
/* Crypto */
/* RX */
int sc_rxbufsize; /* rx size based on mtu */
/* TX */
/* Beacon */
struct ath9k_tx_queue_info sc_beacon_qi;
/* Rate */
/* mode */
/* Channel, Band */
struct ath9k_channel sc_curchan;
/* Locks */
/* LEDs */
/* Rfkill */
/* ANI */
/* interface statistics */
int, int, uint32_t);
};
int ath_cabq_update(struct arn_softc *);
/*
* Read and write, they both share the same lock. We do this to serialize
* reads and writes on Atheros 802.11n PCI devices only. This is required
* as the FIFO on these devices can only accept sanely 2 requests. After
* from happening.
*/
void
unsigned int
#ifdef __cplusplus
}
#endif
#endif /* _ARN_CORE_H */