/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARN_CORE_H
#define _ARN_CORE_H
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/net80211.h>
#include "arn_ath9k.h"
#include "arn_rc.h"
struct ath_node;
/*
* Node type of wifi device
*/
#ifndef DDI_NT_NET_WIFI
#endif
#define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0]))
#define ARN_MIN(a, b) ((a) < (b) ? (a) : (b))
#define ARN_MAX(a, b) ((a) > (b) ? (a) : (b))
#define abs(x) ((x) >= 0 ? (x) : -(x))
enum ath9k_key_len {
};
/*
* Sync a DMA area described by a dma_area_t
*/
/*
* Insert src list after dst list. reinitialize src list thereafter.
*/
static __inline__ void
/* LINTED E_STATIC_UNUSED */
{
if (list_empty(src))
return;
/* reinitialize src list */
}
#define ARN_LE_READ_16(p) \
((uint16_t) \
#define ARN_LE_READ_32(p) \
((uint32_t) \
<< 32) | \
/* Bit map related macros. */
/* Macro to expand scalars to 64-bit objects */
(((unsigned long long int)(x)) & (0xff)) : \
(sizeof (x) == 16) ? \
(((unsigned long long int)(x)) & 0xffff) : \
((sizeof (x) == 32) ? \
(((unsigned long long int)(x)) & 0xffffffff) : \
(unsigned long long int)(x))
/* increment with wrap-around */
(_l)++; \
} while (0)
/* decrement with wrap-around */
(_l)--; \
} while (0)
#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
(IEEE80211_IS_CHAN_5GHZ(_c) && \
(IEEE80211_IS_CHAN_2GHZ(_c) && \
IEEE80211_FC0_SUBTYPE_QOS)) == \
/* Debugging */
enum ARN_DEBUG {
};
/* Debug and log functions */
#ifdef DEBUG
{ command; } \
} while (0)
#else
#endif /* DEBUG */
struct ath_stats {
};
struct dma_area {
/* >= product of above */
};
/* Load-time Configuration */
/*
* Per-instance load-time (note: NOT run-time)
* configurations for Atheros Device
*/
struct ath_config {
};
/* Descriptor Management */
sizeof (struct ath_buf_state)); \
sizeof (struct ath_tx_info_priv)); \
} while (0)
enum buffer_type {
};
struct ath_buf_state {
/* key type used to encrypt this frame */
};
/*
* There is only a single hw descriptor encapsulated here.
*/
struct ath_buf {
/* last buf of this unit (a frame or an aggregate) */
/* Temp workground for rc */
/* we're in list of sc->sc_txbuf_list or sc->sc_rxbuf_list */
};
/*
* reset the rx buffer.
* any new fields added to the athbuf and require
* reset need to be added to this macro.
* currently bf_status is the only one requires that
* requires reset.
*/
/* hw processing complete, desc processed by hal */
/* hw processing complete, desc hold for hw */
/* Rx-only: OS is done with this packet and it's ok to queued it to hw */
/* RX / TX */
/* max number of transmit attempts (tries) */
/* max number of 11n transmit attempts (tries) */
/* max number of tries for management and control frames */
/* Wireless Multimedia Extension Defines */
/*
* Data transmit queue state. One of these exists for each
* hardware transmit queue. Packets sent to us from above
* are assigned to queues based on their priority. Not all
* devices support a complete set of hardware transmit queues.
* For those devices the array sc_ac2q will map multiple
* priorities to fewer hardware queues (typically all to one
* hardware queue).
*/
struct ath_txq {
/* first desc of the last descriptor that contains CTS */
/*
* final desc of the gating desc that determines whether
* lastdsWithCTS has been DMA'ed or not
*/
};
/* per TID aggregate tx state for a destination */
struct ath_atx_tid {
int tidno;
int sched;
int paused;
};
/* per access-category aggregate tx state for a destination */
struct ath_atx_ac {
};
/* per dest tx state */
struct ath_atx {
};
/* per-frame tx control block */
struct ath_tx_control {
int if_id;
};
/* per frame tx status block */
struct ath_xmit_status {
/* number of retries to successufully transmit this frame */
int retries;
};
struct ath_tx_stat {
/* if any of ctl,extn chain rssis are valid */
/* if extn chain rssis are valid */
};
struct ath9k_tx_queue_info *qinfo);
void arn_tx_int_proc(void *arg);
/* Node / Aggregation */
/* number of delimiters for encryption padding */
/* minimum h/w qdepth to be sustained to maximize aggregation */
/*
* return whether a bit at index _n in bitmap _bm is set
* _sz is the size of the bitmap
*/
/* return block-ack bitmap index given sequence and starting sequence */
/* returns delimiter padding required given the packet length */
enum ATH_AGGR_STATUS {
};
struct aggr_rifs_param {
int param_max_frames;
int param_max_len;
int param_rl;
int param_al;
};
/* RSSI correction */
((x != ATH_RSSI_DUMMY_MARKER) ? \
#define ATH_RSSI_LPF(x, y) do { \
if ((y) >= RSSI_LPF_THRESHOLD) \
} while (0)
/* driver-specific node state */
struct ath_node {
int last_rssi;
};
/*
* Define the scheme that we select MAC address for multiple
* BSS on the same radio. The very first VAP will just use the MAC
* address from the EEPROM. For the next 3 VAPs, we set the
* U/L bit (bit 1) in MAC address, and use the next two bits as the
* index of the VAP.
*/
/* driver-specific vap state */
struct ath_vap {
};
/* Beacon Handling */
/*
* Regardless of the number of beacons we stagger, (i.e. regardless of the
* number of BSSIDs) if a given beacon does not go out even after waiting this
* number of beacon intervals, the game's up.
*/
/* beacon configuration */
struct ath_beacon_config {
union {
};
void arn_bmiss_proc(void *arg);
/* ANI */
/*
* ANI values for STA only.
* FIXME: Add appropriate values for AP later
*/
struct ath_ani {
unsigned int sc_longcal_timer;
unsigned int sc_shortcal_timer;
unsigned int sc_resetcal_timer;
unsigned int sc_checkani_timer;
};
/* LED Control */
enum ath_led_type {
};
struct ath_led {
};
/* Rfkill */
/* Main driver core */
/*
* Default cache line size, in bytes.
*/
/*
* The key cache is used for h/w cipher state and also for
* tracking station state such as the current tx antenna.
* We also setup a mapping table between key cache slot indices
* and station state to short-circuit node lookups on rx.
* Different parts have different size key caches. We handle
* up to ATH_KEYMAX entries (could dynamically allocate state).
*/
#define ATH_RATE_DUMMY_MARKER 0
enum PROT_MODE {
PROT_M_NONE = 0,
};
/* HT */
typedef struct ht_conf {
} arn_ht_conf;
struct arn_softc {
int, int, uint16_t[4]);
/* descriptor structure */
/* pointer to the first "struct ath_buf" */
/* length of all allocated "struct ath_buf" */
int sc_debug;
unsigned int rx_filter;
int sc_slottime;
enum {
/* Crypto */
/* RX */
/* TX */
/* Beacon */
/* Rate */
/* mode */
/* Channel, Band */
/* Locks */
/* LEDs */
/* Rfkill */
/* ANI */
/* interface statistics */
int, int, uint32_t);
};
int ath_cabq_update(struct arn_softc *);
/*
* Read and write, they both share the same lock. We do this to serialize
* reads and writes on Atheros 802.11n PCI devices only. This is required
* as the FIFO on these devices can only accept sanely 2 requests. After
* from happening.
*/
void
unsigned int
#ifdef __cplusplus
}
#endif
#endif /* _ARN_CORE_H */