arn_ath9k.h revision 3ae945c326c1fc078149f2c8b11fac0cc8f6d1d6
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARN_ATH9K_H
#define _ARN_ATH9K_H
#ifdef __cplusplus
extern "C" {
#endif
#define FUDGE 2
enum ath9k_band {
};
#define ATHEROS_VENDOR_ID 0x168c
#define AR5416_DEVID_PCI 0x0023
#define AR5416_DEVID_PCIE 0x0024
#define AR9160_DEVID_PCI 0x0027
#define AR9280_DEVID_PCI 0x0029
#define AR9280_DEVID_PCIE 0x002a
#define AR9285_DEVID_PCIE 0x002b
#define AR5416_AR9100_DEVID 0x000b
#define AR_SUBVENDOR_ID_NOG 0x0e11
#define AR_SUBVENDOR_ID_NEW_A 0x7065
#define ATH9K_TXERR_XRETRY 0x01
#define ATH9K_TXERR_FILT 0x02
#define ATH9K_TXERR_FIFO 0x04
#define ATH9K_TXERR_XTXOP 0x08
#define ATH9K_TXERR_TIMER_EXPIRED 0x10
#define ATH9K_TX_BA 0x01
#define ATH9K_TX_PWRMGMT 0x02
#define ATH9K_TX_DESC_CFG_ERR 0x04
#define ATH9K_TX_DATA_UNDERRUN 0x08
#define ATH9K_TX_DELIM_UNDERRUN 0x10
#define ATH9K_TX_SW_ABORTED 0x40
#define ATH9K_TX_SW_FILTERED 0x80
/* should be changed later */
#define BIT(n) (1UL << (n))
struct ath_tx_status {
};
struct ath_rx_status {
};
#define ATH9K_RXERR_CRC 0x01
#define ATH9K_RXERR_PHY 0x02
#define ATH9K_RXERR_FIFO 0x04
#define ATH9K_RXERR_DECRYPT 0x08
#define ATH9K_RXERR_MIC 0x10
#define ATH9K_RX_MORE 0x01
#define ATH9K_RX_MORE_AGGR 0x02
#define ATH9K_RX_GI 0x04
#define ATH9K_RX_2040 0x08
#define ATH9K_RX_DELIM_CRC_PRE 0x10
#define ATH9K_RX_DELIM_CRC_POST 0x20
#define ATH9K_RX_DECRYPT_BUSY 0x40
#pragma pack(1)
struct ath_desc {
union {
struct ath_tx_status tx;
struct ath_rx_status rx;
void *stats;
} ds_us;
void *ds_vdata;
};
#pragma pack()
#define ATH9K_TXDESC_CLRDMASK 0x0001
#define ATH9K_TXDESC_NOACK 0x0002
#define ATH9K_TXDESC_RTSENA 0x0004
#define ATH9K_TXDESC_CTSENA 0x0008
/*
* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
* the descriptor its marked on. We take a tx interrupt to reap
* descriptors when the h/w hits an EOL condition or
* when the descriptor is specifically marked to generate
* an interrupt with this flag. Descriptors should be
* marked periodically to insure timely replenishing of the
* supply needed for sending frames. Defering interrupts
* reduces system load and potentially allows more concurrent
* work to be done but if done to aggressively can cause
* senders to backup. When the hardware queue is left too
* large rate control information may also be too out of
* date. An Alternative for this is TX interrupt mitigation
* but this needs more testing.
*/
#define ATH9K_TXDESC_INTREQ 0x0010
#define ATH9K_TXDESC_VEOL 0x0020
#define ATH9K_TXDESC_EXT_ONLY 0x0040
#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
#define ATH9K_TXDESC_VMF 0x0100
#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
#define ATH9K_TXDESC_CAB 0x0400
#define ATH9K_RXDESC_INTREQ 0x0020
enum wireless_mode {
ATH9K_MODE_11A = 0,
ATH9K_MODE_11B = 2,
ATH9K_MODE_11G = 3,
ATH9K_MODE_11NA_HT20 = 6,
ATH9K_MODE_11NG_HT20 = 7,
ATH9K_MODE_11NG_HT40PLUS = 10,
};
enum ath9k_hw_caps {
ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
};
enum ath9k_capability_type {
ATH9K_CAP_CIPHER = 0,
};
struct ath9k_hw_capabilities {
};
struct ath9k_ops_config {
int ack_6mb;
int cwm_ignore_extcca;
int pcie_power_reset;
int serialize_regmode;
int intr_mitigation;
#define SPUR_DISABLE 0
#define SPUR_ENABLE_IOCTL 1
#define SPUR_ENABLE_EEPROM 2
#define AR_EEPROM_MODAL_SPURS 5
#define AR_SPUR_5413_1 1640
#define AR_SPUR_5413_2 1200
#define AR_NO_SPUR 0x8000
#define AR_BASE_FREQ_2GHZ 2300
#define AR_BASE_FREQ_5GHZ 4900
#define AR_SPUR_FEEQ_BOUND_HT40 19
#define AR_SPUR_FEEQ_BOUND_HT20 10
int spurmode;
};
enum ath9k_tx_queue {
};
#define ATH9K_NUM_TX_QUEUES 10
enum ath9k_tx_queue_subtype {
ATH9K_WME_AC_BK = 0,
};
enum ath9k_tx_queue_flags {
TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
};
#define ATH9K_DECOMP_MASK_SIZE 128
#define ATH9K_READY_TIME_LO_BOUND 50
#define ATH9K_READY_TIME_HI_BOUND 96
enum ath9k_pkt_type {
};
struct ath9k_tx_queue_info {
enum ath9k_tx_queue tqi_type;
};
enum ath9k_rx_filter {
ATH9K_RX_FILTER_UCAST = 0x00000001,
ATH9K_RX_FILTER_MCAST = 0x00000002,
ATH9K_RX_FILTER_BCAST = 0x00000004,
ATH9K_RX_FILTER_CONTROL = 0x00000008,
ATH9K_RX_FILTER_BEACON = 0x00000010,
ATH9K_RX_FILTER_PROM = 0x00000020,
ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
ATH9K_RX_FILTER_PSPOLL = 0x00004000,
ATH9K_RX_FILTER_PHYERR = 0x00000100,
ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
};
enum ath9k_int {
ATH9K_INT_RX = 0x00000001,
ATH9K_INT_RXDESC = 0x00000002,
ATH9K_INT_RXNOFRM = 0x00000008,
ATH9K_INT_RXEOL = 0x00000010,
ATH9K_INT_RXORN = 0x00000020,
ATH9K_INT_TX = 0x00000040,
ATH9K_INT_TXDESC = 0x00000080,
ATH9K_INT_TIM_TIMER = 0x00000100,
ATH9K_INT_TXURN = 0x00000800,
ATH9K_INT_MIB = 0x00001000,
ATH9K_INT_RXPHY = 0x00004000,
ATH9K_INT_RXKCM = 0x00008000,
ATH9K_INT_SWBA = 0x00010000,
ATH9K_INT_BMISS = 0x00040000,
ATH9K_INT_BNR = 0x00100000,
ATH9K_INT_TIM = 0x00200000,
ATH9K_INT_DTIM = 0x00400000,
ATH9K_INT_DTIMSYNC = 0x00800000,
ATH9K_INT_GPIO = 0x01000000,
ATH9K_INT_CABEND = 0x02000000,
ATH9K_INT_CST = 0x10000000,
ATH9K_INT_GTT = 0x20000000,
ATH9K_INT_FATAL = 0x40000000,
ATH9K_INT_NOCARD = -1
};
#define ATH9K_RATESERIES_RTS_CTS 0x0001
#define ATH9K_RATESERIES_2040 0x0002
#define ATH9K_RATESERIES_HALFGI 0x0004
struct ath9k_11n_rate_series {
};
#define CHANNEL_CW_INT 0x00002
#define CHANNEL_CCK 0x00020
#define CHANNEL_OFDM 0x00040
#define CHANNEL_2GHZ 0x00080
#define CHANNEL_5GHZ 0x00100
#define CHANNEL_PASSIVE 0x00200
#define CHANNEL_DYN 0x00400
#define CHANNEL_HALF 0x04000
#define CHANNEL_QUARTER 0x08000
#define CHANNEL_HT20 0x10000
#define CHANNEL_HT40PLUS 0x20000
#define CHANNEL_HT40MINUS 0x40000
#define CHANNEL_INTERFERENCE 0x01
#define CHANNEL_DFS 0x02
#define CHANNEL_4MS_LIMIT 0x04
#define CHANNEL_DFS_CLEAR 0x08
#define CHANNEL_DISALLOW_ADHOC 0x10
#define CHANNEL_PER_11D_ADHOC 0x20
#define CHANNEL_ALL \
(CHANNEL_OFDM| \
CHANNEL_CCK| \
CHANNEL_2GHZ | \
CHANNEL_5GHZ | \
CHANNEL_HT20 | \
CHANNEL_HT40PLUS | \
struct ath9k_channel {
#ifdef ARN_NF_PER_CHAN
#endif
};
#define IS_CHAN_QUARTER_RATE(_c) \
/* These macros check chanmode and not channelFlags */
#define IS_CHAN_A_5MHZ_SPACED(_c) \
struct ath9k_keyval {
};
enum ath9k_key_type {
};
enum ath9k_cipher {
ATH9K_CIPHER_WEP = 0,
ATH9K_CIPHER_AES_OCB = 1,
ATH9K_CIPHER_AES_CCM = 2,
ATH9K_CIPHER_CKIP = 3,
ATH9K_CIPHER_TKIP = 4,
ATH9K_CIPHER_CLR = 5,
ATH9K_CIPHER_MIC = 127
};
#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
#define AR_EEPROM_EEPCAP_MAXQCU_S 4
#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
#define SD_NO_CTL 0xE0
#define NO_CTL 0xff
#define CTL_MODE_M 7
#define CTL_11A 0
#define CTL_11B 1
#define CTL_11G 2
#define CTL_2GHT20 5
#define CTL_5GHT20 6
#define CTL_2GHT40 7
#define CTL_5GHT40 8
#define AR_EEPROM_MAC(i) (0x1d+(i))
#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
#define AR_EEPROM_RFSILENT_POLARITY 0x0002
#define AR_EEPROM_RFSILENT_POLARITY_S 1
#define CTRY_DEBUG 0x1ff
#define CTRY_DEFAULT 0
enum reg_ext_bitmap {
REG_EXT_FCC_DFS_HT40 = 2,
};
struct ath9k_country_entry {
};
#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
#define INIT_AIFS 2
#define INIT_CWMIN 15
#define INIT_CWMIN_11B 31
#define INIT_CWMAX 1023
#define INIT_SH_RETRY 10
#define INIT_LG_RETRY 10
#define INIT_SSH_RETRY 32
#define INIT_SLG_RETRY 32
#define IEEE80211_WEP_IVLEN 3
#define IEEE80211_WEP_KIDLEN 1
#define IEEE80211_WEP_CRCLEN 4
(IEEE80211_WEP_IVLEN + \
#define MAX_RATE_POWER 63
enum ath9k_power_mode {
ATH9K_PM_AWAKE = 0,
};
struct ath9k_mib_stats {
};
enum ath9k_ant_setting {
ATH9K_ANT_VARIABLE = 0,
};
enum ath9k_opmode {
ATH9K_M_STA = 1,
ATH9K_M_IBSS = 0,
ATH9K_M_HOSTAP = 6,
ATH9K_M_MONITOR = 8
};
#define ATH9K_SLOT_TIME_6 6
#define ATH9K_SLOT_TIME_9 9
#define ATH9K_SLOT_TIME_20 20
enum ath9k_ht_macmode {
ATH9K_HT_MACMODE_20 = 0,
};
enum ath9k_ht_extprotspacing {
};
struct ath9k_ht_cwm {
enum ath9k_ht_macmode ht_macmode;
};
enum ath9k_ani_cmd {
ATH9K_ANI_PRESENT = 0x1,
ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
ATH9K_ANI_MODE = 0x40,
ATH9K_ANI_PHYERR_RESET = 0x80,
ATH9K_ANI_ALL = 0xff
};
enum {
};
enum ath9k_tp_scale {
ATH9K_TP_SCALE_MAX = 0,
};
enum ser_reg_mode {
SER_REG_MODE_OFF = 0,
SER_REG_MODE_ON = 1,
SER_REG_MODE_AUTO = 2,
};
#define AR_PHY_CCA_MAX_GOOD_VALUE -85
#define AR_PHY_CCA_MAX_HIGH_VALUE -62
#define AR_PHY_CCA_MIN_BAD_VALUE -121
#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
#define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
#define ATH9K_NF_CAL_HIST_MAX 5
#define NUM_NF_READINGS 6
struct ath9k_nfcal_hist {
};
struct ath9k_beacon_state {
#define ATH9K_BEACON_PERIOD 0x0000ffff
#define ATH9K_BEACON_ENA 0x00800000
#define ATH9K_BEACON_RESET_TSF 0x01000000
};
struct ath9k_node_stats {
};
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
enum {
};
#define AH_USE_EEPROM 0x1
struct ath_hal {
enum ath9k_opmode ah_opmode;
struct ath9k_ops_config ah_config;
struct ath9k_hw_capabilities ah_caps;
char ah_iso[4];
struct ath9k_channel *ah_curchan;
#ifndef ARN_NF_PER_CHAN
#endif
};
struct chan_centers {
};
struct ath_rate_table;
/* Helpers */
const struct ath9k_channel *chan);
struct ath_rate_table *rates,
struct ath9k_channel *chan,
struct chan_centers *centers);
/* Attach, Detach */
/* HW Reset */
enum ath9k_ht_macmode macmode,
/* Key Cache Management */
/* Power Management */
enum ath9k_power_mode mode);
/* Beacon timers */
const struct ath9k_beacon_state *bs);
/* HW Capabilities */
enum ath9k_capability_type type,
enum ath9k_capability_type type,
int *status);
/* GPIO / RFKILL / Antennae */
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
#endif
enum ath9k_ant_setting settings,
struct ath9k_channel *chan,
/* General Operation */
/* Regulatory */
const struct ath9k_channel *c);
struct ath9k_channel *chan);
/* ANI */
const struct ath9k_node_stats *stats,
struct ath9k_channel *chan);
const struct ath9k_node_stats *stats);
/* Calibration */
struct ath9k_channel *chan);
struct ath9k_channel *chan);
/* EEPROM */
struct ath9k_channel *chan,
struct ath9k_channel *chan,
struct ath9k_channel *chan);
enum ath9k_band freq_band);
/* Interrupt Handling */
struct ath9k_11n_rate_series series[],
const struct ath9k_tx_queue_info *qinfo);
struct ath9k_tx_queue_info *qinfo);
const struct ath9k_tx_queue_info *qinfo);
#ifdef __cplusplus
}
#endif
#endif /* _ARN_ATH9K_H */