/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARN_ATH9K_H
#define _ARN_ATH9K_H
#ifdef __cplusplus
extern "C" {
#endif
enum ath9k_band {
};
/* should be changed later */
struct ath_tx_status {
};
struct ath_rx_status {
};
#pragma pack(1)
struct ath_desc {
union {
void *stats;
} ds_us;
void *ds_vdata;
};
#pragma pack()
/*
* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
* the descriptor its marked on. We take a tx interrupt to reap
* descriptors when the h/w hits an EOL condition or
* when the descriptor is specifically marked to generate
* an interrupt with this flag. Descriptors should be
* marked periodically to insure timely replenishing of the
* supply needed for sending frames. Defering interrupts
* reduces system load and potentially allows more concurrent
* work to be done but if done to aggressively can cause
* senders to backup. When the hardware queue is left too
* large rate control information may also be too out of
* date. An Alternative for this is TX interrupt mitigation
* but this needs more testing.
*/
enum wireless_mode {
ATH9K_MODE_11A = 0,
};
enum ath9k_hw_caps {
};
enum ath9k_capability_type {
ATH9K_CAP_CIPHER = 0,
};
struct ath9k_hw_capabilities {
};
struct ath9k_ops_config {
int ack_6mb;
int cwm_ignore_extcca;
int pcie_power_reset;
int serialize_regmode;
int intr_mitigation;
#define SPUR_DISABLE 0
int spurmode;
};
enum ath9k_tx_queue {
};
enum ath9k_tx_queue_subtype {
ATH9K_WME_AC_BK = 0,
};
enum ath9k_tx_queue_flags {
};
enum ath9k_pkt_type {
};
struct ath9k_tx_queue_info {
};
enum ath9k_rx_filter {
};
enum ath9k_int {
};
struct ath9k_11n_rate_series {
};
#define CHANNEL_ALL \
(CHANNEL_OFDM| \
CHANNEL_CCK| \
CHANNEL_2GHZ | \
CHANNEL_5GHZ | \
CHANNEL_HT20 | \
CHANNEL_HT40PLUS | \
struct ath9k_channel {
#ifdef ARN_NF_PER_CHAN
#endif
};
/* These macros check chanmode and not channelFlags */
struct ath9k_keyval {
};
enum ath9k_key_type {
};
enum ath9k_cipher {
ATH9K_CIPHER_WEP = 0,
};
#define CTL_11A 0
#define CTRY_DEFAULT 0
enum reg_ext_bitmap {
};
struct ath9k_country_entry {
};
(IEEE80211_WEP_IVLEN + \
enum ath9k_power_mode {
ATH9K_PM_AWAKE = 0,
};
struct ath9k_mib_stats {
};
enum ath9k_ant_setting {
ATH9K_ANT_VARIABLE = 0,
};
enum ath9k_opmode {
ATH9K_M_IBSS = 0,
};
enum ath9k_ht_macmode {
ATH9K_HT_MACMODE_20 = 0,
};
enum ath9k_ht_extprotspacing {
};
struct ath9k_ht_cwm {
};
enum ath9k_ani_cmd {
};
enum ath9k_tp_scale {
ATH9K_TP_SCALE_MAX = 0,
};
enum ser_reg_mode {
SER_REG_MODE_OFF = 0,
};
struct ath9k_nfcal_hist {
};
struct ath9k_beacon_state {
};
struct ath9k_node_stats {
};
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
enum {
};
struct ath_hal {
};
struct chan_centers {
};
struct ath_rate_table;
/* Helpers */
const struct ath9k_channel *chan);
struct ath_rate_table *rates,
struct ath9k_channel *chan,
struct chan_centers *centers);
/* Attach, Detach */
/* HW Reset */
enum ath9k_ht_macmode macmode,
/* Key Cache Management */
/* Power Management */
enum ath9k_power_mode mode);
/* Beacon timers */
const struct ath9k_beacon_state *bs);
/* HW Capabilities */
enum ath9k_capability_type type,
enum ath9k_capability_type type,
int *status);
/* GPIO / RFKILL / Antennae */
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
#endif
enum ath9k_ant_setting settings,
struct ath9k_channel *chan,
/* General Operation */
/* Regulatory */
const struct ath9k_channel *c);
struct ath9k_channel *chan);
/* ANI */
const struct ath9k_node_stats *stats,
struct ath9k_channel *chan);
const struct ath9k_node_stats *stats);
/* Calibration */
struct ath9k_channel *chan);
struct ath9k_channel *chan);
/* EEPROM */
struct ath9k_channel *chan,
struct ath9k_channel *chan,
struct ath9k_channel *chan);
enum ath9k_band freq_band);
/* Interrupt Handling */
struct ath9k_11n_rate_series series[],
const struct ath9k_tx_queue_info *qinfo);
struct ath9k_tx_queue_info *qinfo);
const struct ath9k_tx_queue_info *qinfo);
#ifdef __cplusplus
}
#endif
#endif /* _ARN_ATH9K_H */