/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 2001 by Sun Microsystems, Inc.
* All rights reserved.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/promimpl.h>
/*
* This file contains the implementations of all Starfire-specific
* promif routines.
*/
/*
* Probe all of the devices on a board. The board number is
* computed from cpuid. All of the cpus on the board are
* brought into OBP's slave idle loop but are not started.
* Returns zero for success and non-zero for failure.
*/
int
{
int rv;
}
/*
* Prune the device tree nodes for all devices on the board
* represented by brdnum. Returns zero for success and non-zero
* for failure.
*/
int
{
int rv;
}
/*
* Prepare firmware internal state for the inclusion of the
* cpu represented by cpuid. This operation has no effect on
* the cpu hardware or behavior in the client.
*/
void
{
(void) p1275_cif_handler(&ci);
}
/*
* Prepare firmware internal state for the departure of the cpu
* represented by cpuid.
*/
void
{
(void) p1275_cif_handler(&ci);
}
/*
* Mark the cpu represented by cpuid as cpu0. Returns zero for
* success and non-zero for failure.
*/
int
{
int rv;
}
/*
* Perform initialization steps required for the console before
* moving cpu0. The console uses the bootbus SRAM of cpu0 for both
* input and output. The offsets of the console buffers are initialized
* for the bootbus SRAM of the new cpu0 represented by cpuid.
*/
void
{
(void) p1275_cif_handler(&ci);
}