libcpc_impl.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2004 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _LIBCPC_IMPL_H
#define _LIBCPC_IMPL_H
#pragma ident "%Z%%M% %I% %E% SMI"
#include <libcpc.h>
#include <inttypes.h>
#include <thread.h>
#include <synch.h>
#include <sys/cpc_impl.h>
#ifdef __cplusplus
extern "C" {
#endif
#define CPC_VER_1 1
struct _cpc_attr {
char ca_name[CPC_MAX_ATTR_LEN];
};
typedef struct __cpc_request cpc_request_t;
struct __cpc_request {
char cr_event[CPC_MAX_EVENT_LEN];
};
struct __cpc_buf {
};
/*
* Possible cpc_set_t states:
*/
typedef enum {
CS_UNBOUND, /* Set is not currently bound */
CS_BOUND_CURLWP, /* Set has been bound to curlwp */
CS_BOUND_PCTX, /* Set has been bound via libpctx */
CS_BOUND_CPU /* Set has been bound to a CPU */
struct __cpc_set {
int cs_nreqs; /* Number of requests in set */
int cs_fd; /* file descriptor of cpc dev */
};
struct __cpc {
char *cpc_attrlist; /* List of supported attrs */
char **cpc_evlist; /* List of events per pic */
char cpc_cpuref[CPC_MAX_CPUREF];
char cpc_cciname[CPC_MAX_IMPL_NAME];
};
/*
* cpc_t handle for CPCv1 clients.
*/
/*PRINTFLIKE2*/
extern uint_t __cpc_workver;
extern int __cpc_v1_cpuver;
#ifdef __sparc
extern uint64_t __cpc_v1_pcr;
#else
#endif /* __sparc */
typedef struct __cpc_strhash cpc_strhash_t;
struct __cpc_strhash {
char *str;
struct __cpc_strhash *cur;
struct __cpc_strhash *next;
};
extern cpc_strhash_t *__cpc_strhash_alloc(void);
/*
* Implementation-private system call used by libcpc
*/
struct __cpc;
/*
* These two are only used for backwards compatibility to the Obsolete CPCv1.
*/
extern int __cpc_init(void);
/*
* ce_cpuver values
*/
#define CPC_ULTRA1 1000
#define CPC_ULTRA3 1002
#define CPC_ULTRA3_PLUS 1003
#define CPC_ULTRA3_I 1004
#define CPC_PENTIUM 2000
#define CPC_PENTIUM_MMX 2001
#define CPC_PENTIUM_PRO 2002
#define CPC_PENTIUM_PRO_MMX 2003
#define CPC_SPARC64_III 3000
#define CPC_SPARC64_V 3002
#endif /* __sparc || __i386 */
/*
* This is common between i386 and amd64, because amd64 implements %tick.
* Currently only used by the cpc tools to print the label atop the CPU ticks
* column on amd64.
*/
#define CPC_TICKREG_NAME "tsc"
#endif /* __i386 || __amd64 */
#if defined(__sparc)
/*
* UltraSPARC I, II and III processors
*
* The performance counters on these processors allow up to two 32-bit
* performance events to be captured simultaneously from a selection
* of metrics. The metrics are selected by writing to the performance
* control register, and subsequent values collected by reading from the
* performance instrumentation counter registers. Both registers are
* priviliged by default, and implemented as ASRs.
*/
struct _cpc_event {
int ce_cpuver;
};
#define CPC_TICKREG_NAME "%tick"
/*
* "Well known" bitfields in the UltraSPARC %pcr register
* The interfaces in libcpc should make these #defines uninteresting.
*/
#define CPC_ULTRA_PCR_USR 2
#define CPC_ULTRA_PCR_SYS 1
#define CPC_ULTRA_PCR_PRIVPIC 0
#define CPC_ULTRA_PCR_PIC0_SHIFT 4
#define CPC_ULTRA_PCR_PIC1_SHIFT 11
/*
* Pentium I, II and III processors
*
* These CPUs allow pairs of events to captured.
* The hardware counters count up to 40-bits of significance, but
* only allow 32 (signed) bits to be programmed into them.
* Pentium I and Pentium II processors are programmed differently, but
* the resulting counters and timestamps can be handled portably.
*/
struct _cpc_event {
int ce_cpuver;
};
/*
* "Well known" bit fields in the Pentium CES register
* The interfaces in libcpc should make these #defines uninteresting.
*/
#define CPC_P5_CESR_ES0_SHIFT 0
#define CPC_P5_CESR_ES0_MASK 0x3f
#define CPC_P5_CESR_ES1_SHIFT 16
#define CPC_P5_CESR_ES1_MASK 0x3f
#define CPC_P5_CESR_OS0 6
#define CPC_P5_CESR_USR0 7
#define CPC_P5_CESR_CLK0 8
#define CPC_P5_CESR_PC0 9
/*
* "Well known" bit fields in the Pentium Pro PerfEvtSel registers
* The interfaces in libcpc should make these #defines uninteresting.
*/
#define CPC_P6_PES_INV 23
#define CPC_P6_PES_EN 22
#define CPC_P6_PES_INT 20
#define CPC_P6_PES_PC 19
#define CPC_P6_PES_E 18
#define CPC_P6_PES_OS 17
#define CPC_P6_PES_USR 16
#define CPC_P6_PES_UMASK_SHIFT 8
#define CPC_P6_PES_UMASK_MASK (0xffu)
#define CPC_P6_PES_CMASK_SHIFT 24
#define CPC_P6_PES_CMASK_MASK (0xffu)
#define CPC_P6_PES_PIC0_MASK (0xffu)
#define CPC_P6_PES_PIC1_MASK (0xffu)
#endif /* __i386 */
#ifdef __cplusplus
}
#endif
#endif /* _LIBCPC_IMPL_H */