/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _LIBCPC_IMPL_H
#define _LIBCPC_IMPL_H
#pragma ident "%Z%%M% %I% %E% SMI"
#include <libcpc.h>
#include <inttypes.h>
#include <thread.h>
#include <synch.h>
#include <sys/cpc_impl.h>
#ifdef __cplusplus
extern "C" {
#endif
struct _cpc_attr {
};
struct __cpc_request {
};
struct __cpc_buf {
};
/*
* Possible cpc_set_t states:
*/
typedef enum {
struct __cpc_set {
};
struct __cpc {
};
/*
* cpc_t handle for CPCv1 clients.
*/
/*PRINTFLIKE2*/
extern uint_t __cpc_workver;
extern int __cpc_v1_cpuver;
#ifdef __sparc
extern uint64_t __cpc_v1_pcr;
#else
#endif /* __sparc */
struct __cpc_strhash {
char *str;
};
extern cpc_strhash_t *__cpc_strhash_alloc(void);
/*
* Implementation-private system call used by libcpc
*/
struct __cpc;
/*
* These two are only used for backwards compatibility to the Obsolete CPCv1.
*/
extern int __cpc_init(void);
/*
* ce_cpuver values
*/
#endif /* __sparc || __i386 */
/*
* This is common between i386 and amd64, because amd64 implements %tick.
* Currently only used by the cpc tools to print the label atop the CPU ticks
* column on amd64.
*/
#endif /* __i386 || __amd64 */
#if defined(__sparc)
/*
* UltraSPARC I, II, III and IV processors
*
* The performance counters on these processors allow up to two 32-bit
* performance events to be captured simultaneously from a selection
* of metrics. The metrics are selected by writing to the performance
* control register, and subsequent values collected by reading from the
* performance instrumentation counter registers. Both registers are
* priviliged by default, and implemented as ASRs.
*/
struct _cpc_event {
int ce_cpuver;
};
/*
* "Well known" bitfields in the UltraSPARC %pcr register
* The interfaces in libcpc should make these #defines uninteresting.
*/
#define CPC_ULTRA_PCR_PRIVPIC 0
/*
* Pentium I, II and III processors
*
* These CPUs allow pairs of events to captured.
* The hardware counters count up to 40-bits of significance, but
* only allow 32 (signed) bits to be programmed into them.
* Pentium I and Pentium II processors are programmed differently, but
* the resulting counters and timestamps can be handled portably.
*/
struct _cpc_event {
int ce_cpuver;
};
/*
* "Well known" bit fields in the Pentium CES register
* The interfaces in libcpc should make these #defines uninteresting.
*/
#define CPC_P5_CESR_ES0_SHIFT 0
/*
* "Well known" bit fields in the Pentium Pro PerfEvtSel registers
* The interfaces in libcpc should make these #defines uninteresting.
*/
#endif /* __i386 */
#ifdef __cplusplus
}
#endif
#endif /* _LIBCPC_IMPL_H */