#endif
#endif
/* Offsets to registers (using SMC names). */
GENCTL =
0x0C,
/* General Control */ NVCTL =
0x10,
/* Non Volatile Control */ EECTL =
0x14,
/* EEPROM Control */ TEST =
0x1C,
/* Test register: marked as reserved (see in source code) */ CRCCNT =
0x20,
/* CRC Error Counter */ ALICNT =
0x24,
/* Frame Alignment Error Counter */ MPCNT =
0x28,
/* Missed Packet Counter */ MMCTL =
0x30,
/* MII Management Interface Control */ MMDATA =
0x34,
/* MII Management Interface Data */ MIICFG =
0x38,
/* MII Configuration */ IPG =
0x3C,
/* InterPacket Gap */ LAN0 =
0x40,
/* MAC address. (0x40-0x48) */ IDCHK =
0x4C,
/* BoardID/ Checksum */ MC0 =
0x50,
/* Multicast filter table. (0x50-0x5c) */ RXCON =
0x60,
/* Receive Control */ TXCON =
0x70,
/* Transmit Control */ TXSTAT =
0x74,
/* Transmit Status */ PRCDAR =
0x84,
/* PCI Receive Current Descriptor Address */ PRSTAT =
0xA4,
/* PCI Receive DMA Status */ PRCPTHR=
0xB0,
/* PCI Receive Copy Threshold */ PTCDAR =
0xC4,
/* PCI Transmit Current Descriptor Address */ ETHTHR =
0xDC /* Early Transmit Threshold */ };
/* Command register (CR_) bits */
/* Interrupt register bits. NI means No Interrupt generated */
#
define INTR_TXDONE (
0x00000020)
/* tx complete (w or w/o err) */#
define INTR_RXDONE (
0x00000001)
/* Receive copy complete */
/* General Control (GC_) bits */
/*
* Receive FIFO Threshold values
* Control the level at which the PCI burst state machine
* begins to empty the receive FIFO. Possible values: 0-3
*
* 0 => 32, 1 => 64, 2 => 96 3 => 128 bytes.
*/
/* Memory Read Control (MRC_) values */
/* Definitions of the Receive Control (RC_) register bits */
/* description of the rx descriptors control bits */
#
define RD_FRAGLIST (
0x0001)
/* Desc points to a fragment list */#
define RD_LLFORM (
0x0002)
/* Frag list format */#
define RD_HDR_CPY (
0x0004)
/* Desc used for header copy */
/* Definition of the Transmit CONTROL (TC) register bits */
/* Loopback Mode (LM_) Select valuesbits */
/* Bytes transferred to chip before transmission starts. */
/* description of rx descriptors status bits */
/* error summary */
/* description of tx descriptors status bits */
#
define TRING_COLL (
0x0004)
/* pkt xmitted w collisions */#
define TRING_CARR (
0x0008)
/* carrier sense lost */#
define TRING_OWN (
0x8000)
/* desc ownership bit */
/* error summary */
/* description of the tx descriptors control bits */
#
define TD_FRAGLIST (
0x0001)
/* Desc points to a fragment list */#
define TD_LLFORM (
0x0002)
/* Frag list format */#
define TD_IAF (
0x0004)
/* Generate Interrupt after tx */#
define TD_NOCRC (
0x0008)
/* No CRC generated */#
define TD_LASTDESC (
0x0010)
/* Last desc for this frame */
#endif /* _EPIC100_H_ */