/*
* eepro100.c -- This file implements the eepro100 driver for etherboot.
*
*
* Copyright (C) AW Computer Systems.
* written by R.E.Wolff -- R.E.Wolff@BitWizard.nl
*
*
* AW Computer Systems is contributing to the free software community
* by paying for this driver and then putting the result under GPL.
*
* If you need a Linux device driver, please contact BitWizard for a
* quote.
*
*
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
* date version by what
* Written: May 29 1997 V0.10 REW Initial revision.
* changes: May 31 1997 V0.90 REW Works!
* Jun 1 1997 V0.91 REW Cleanup
* Jun 2 1997 V0.92 REW Add some code documentation
* Jul 25 1997 V1.00 REW Tested by AW to work in a PROM
* Cleanup for publication
*
* This is the etherboot intel etherexpress Pro/100B driver.
*
* It was written from scratch, with Donald Beckers eepro100.c kernel
* driver as a guideline. Mostly the 82557 related definitions and the
* lower level routines have been cut-and-pasted into this source.
*
* The driver was finished before Intel got the NDA out of the closet.
* I still don't have the docs.
* */
/* Philosophy of this driver.
*
* Probing:
*
* Using the pci.c functions of the Etherboot code, the 82557 chip is detected.
* It is verified that the BIOS initialized everything properly and if
* something is missing it is done now.
*
*
* Initialization:
*
*
* The chip is then initialized to "know" its ethernet address, and to
* start recieving packets. The Linux driver has a whole transmit and
* recieve ring of buffers. This is neat if you need high performance:
* you can write the buffers asynchronously to the chip reading the
* buffers and transmitting them over the network. Performance is NOT
* an issue here. We can boot a 400k kernel in about two
* seconds. (Theory: 0.4 seconds). Booting a system is going to take
* about half a minute anyway, so getting 10 times closer to the
* theoretical limit is going to make a difference of a few percent.
*
*
* Transmitting and recieving.
*
* We have only one transmit descriptor. It has two buffer descriptors:
* one for the header, and the other for the data.
* We have only one receive buffer. The chip is told to recieve packets,
* and suspend itself once it got one. The recieve (poll) routine simply
* looks at the recieve buffer to see if there is already a packet there.
* if there is, the buffer is copied, and the reciever is restarted.
*
* Caveats:
*
* The Etherboot framework moves the code to the 48k segment from
* 0x94000 to 0xa0000. There is just a little room between the end of
* this driver and the 0xa0000 address. If you compile in too many
* features, this will overflow.
* The number under "hex" in the output of size that scrolls by while
* compiling should be less than 8000. Maybe even the stack is up there,
* so that you need even more headroom.
*/
/* The etherboot authors seem to dislike the argument ordering in
* outb macros that Linux uses. I disklike the confusion that this
* has caused even more.... This file uses the Linux argument ordering. */
/* Sorry not us. It's inherited code from FreeBSD. [The authors] */
#include "etherboot.h"
#include "nic.h"
#include "pci.h"
#include "timer.h"
static int ioaddr;
typedef unsigned char u8;
typedef signed char s8;
typedef unsigned short u16;
typedef signed short s16;
typedef unsigned int u32;
typedef signed int s32;
enum speedo_offsets {
};
enum SCBCmdBits {
/* The rest are Rx and Tx commands. */
};
/***********************************************************************/
/* I82557 related defines */
/***********************************************************************/
/* Serial EEPROM section.
A "bit" grungy, but we work our way through bit-by-bit :->. */
/* EEPROM_Ctrl bits. */
/* The EEPROM commands include the alway-set leading bit. */
/* The SCB accepts the following controls for the Tx and Rx units: */
/* Commands that can be put in a command list entry. */
enum commands {
CmdNOp = 0,
/* And some extra flags: */
};
/* How to wait for the command unit to accept a command.
Typically this takes 0 ticks. */
{
int wait = 0;
int delayed_cmd;
do
if (inb(cmd_ioaddr) == 0) return;
while(++wait <= 100);
do
if (inb(cmd_ioaddr) == 0) break;
while(++wait <= 10000);
printf("Command %2.2x was not immediately accepted, %d ticks!\n",
delayed_cmd, wait);
}
/* Elements of the dump_statistics block. This block must be lword aligned. */
static struct speedo_stats {
} lstats;
/* A speedo3 TX buffer descriptor with two buffers... */
static struct TxFD {
/* This constitutes two "TBD" entries: hdr and data */
} txfd;
};
#define ACCESS(x) x.
/* I don't understand a byte in this structure. It was copied from the
* Linux kernel initialization for the eepro100. -- REW */
static struct ConfCmd {
} confcmd = {
0, 0, 0, /* filled in later */
{22, 0x08, 0, 0, 0, 0x80, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
0, 0x2E, 0, 0x60, 0,
0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
0x3f, 0x05, }
};
/***********************************************************************/
/* Locally used functions */
/***********************************************************************/
/* Support function: mdio_write
*
* This probably writes to the "physical media interface chip".
* -- REW
*/
{
ioaddr + SCBCtrlMDI);
do {
udelay(16);
if (--boguscnt < 0) {
break;
}
} while (! (val & 0x10000000));
return val & 0xffff;
}
/* Support function: mdio_read
*
* This probably reads a register in the "physical media interface chip".
* -- REW
*/
{
do {
udelay(16);
if (--boguscnt < 0) {
break;
}
} while (! (val & 0x10000000));
return val & 0xffff;
}
/* The fixes for the code were kindly provided by Dragan Stancevic
<visitor@valinux.com> to strictly follow Intel specifications of EEPROM
access timing.
The publicly available sheet 64486302 (sec. 3.1) specifies 1us access
interval for serial EEPROM. However, it looks like that there is an
additional requirement dictating larger udelay's in the code below.
2000/05/24 SAW */
{
unsigned retval = 0;
/* Shift the command bits out. */
do {
} while (--cmd_len >= 0);
/* Terminate the EEPROM access. */
return retval;
}
#if 0
{
sleep (2);
}
#else
#define whereami(s)
#endif
{
switch ( action ) {
case DISABLE :
break;
case ENABLE :
break;
case FORCE :
break;
}
}
/* function: eepro100_transmit
* This transmits a packet.
*
* Arguments: char d[6]: destination ethernet address.
* unsigned short t: ethernet protocol type.
* unsigned short s: size of the data-part of the packet.
* char *p: the data for the packet.
* returns: void.
*/
static void eepro100_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)
{
struct eth_hdr {
unsigned short type;
} hdr;
unsigned short status;
/* Acknowledge all of the current interrupt sources ASAP. */
#ifdef DEBUG
printf ("transmitting type %hX packet (%d bytes). status = %hX, cmd=%hX\n",
#endif
txfd.tx_buf_size1 = s;
#ifdef DEBUG
printf ("txfd: \n");
#endif
/* Wait */;
#ifdef DEBUG
#endif
}
/*
* Sometimes the receiver stops making progress. This routine knows how to
* get it going again, without losing packets or being otherwise nasty like
* a chip reset would be. Previously the driver had a whole sequence
* of if RxSuspended, if it's no buffers do one thing, if it's no resources,
* do another, etc. But those things don't really matter. Separate logic
* in the ISR provides for allocating buffers--the other half of operation
* is just making sure the receiver is active. speedo_rx_soft_reset does that.
* This problem with the old, more involved algorithm is shown up under
*/
static void
speedo_rx_soft_reset(void)
{
/*
* Put the hardware into a known state.
*/
}
/* function: eepro100_poll / eth_poll
* This recieves a packet from the network.
*
* Arguments: none
*
* returns: 1 if a packet was recieved.
* 0 if no pacet was recieved.
* side effects:
* returns the packet in the array nic->packet.
* returns the length of the packet in nic->packetlen.
*/
{
unsigned int status;
return 0;
/* There is a packet ready */
if ( ! retrieve ) return 1;
/*
* The chip may have suspended reception for various reasons.
* Check for that, and re-prime it should this be the case.
*/
case 0: /* Idle */
break;
case 1: /* Suspended */
case 2: /* No resources (RxFDs) */
case 9: /* Suspended with no more RBDs */
case 10: /* No resources due to no RBDs */
case 12: /* Ready with no RBDs */
break;
case 3: case 5: case 6: case 7: case 8:
case 11: case 13: case 14: case 15:
/* these are all reserved values */
break;
}
/* Ok. We got a packet. Now restart the reciever.... */
#ifdef DEBUG
#endif
#ifdef DEBUG
#endif
return 1;
}
/* function: eepro100_disable
* resets the card. This is used to allow Etherboot or Linux
* to probe the card again from a "virginal" state....
* Arguments: none
*
* returns: void.
*/
{
/* from eepro100_reset */
/* from eepro100_disable */
/* See if this PartialReset solves the problem with interfering with
kernel operation after Etherboot hands over. - Ken 20001102 */
/* The following is from the Intel e100 driver.
* This hopefully solves the problem with hanging hard DOS images. */
/* wait for the reset to take effect */
udelay(20);
/* Mask off our interrupt line -- it is unmasked after reset */
{
/* Disable interrupts on our PCI board by setting the mask bit */
/* ack and clear intrs */
}
}
/* exported function: eepro100_probe / eth_probe
* initializes a card
*
* side effects:
* leaves the ioaddress of the 82557 chip in the variable ioaddr.
* leaves the 82557 initialized, and ready to recieve packets.
*/
{
unsigned short sum = 0;
int i;
int options;
int rx_mode;
/* we cache only the first few words of the EEPROM data
be careful not to access beyond this array */
if (p->ioaddr == 0)
return 0;
/* Copy IRQ from PCI information */
/* nic->irqno = pci->irq; */
== 0xffe0000) {
ee_size = 0x100;
} else {
ee_size = 0x40;
}
}
for (i=0;i<ETH_ALEN;i++) {
}
if (sum != 0xBABA)
printf("eepro100: Invalid EEPROM checksum %#hX, "
"check settings before activating this device!\n", sum);
udelay (10000);
whereami ("Got eeprom.");
/* Base = 0 */
whereami ("set rx base addr.");
whereami ("set stats addr.");
/* INIT RX stuff. */
whereami ("started RX process.");
/* Start the reciever.... */
/* INIT TX stuff. */
/* Base = 0 */
whereami ("set TX base addr.");
{
char *t = (char *)&txfd.tx_desc_addr;
for (i=0;i<ETH_ALEN;i++)
}
#ifdef DEBUG
printf ("Setup_eaddr:\n");
#endif
/* options = 0x40; */ /* 10mbps half duplex... */
#ifdef PROMISC
rx_mode = 3;
rx_mode = 1;
#else
rx_mode = 0;
#endif
if (congenb)
mdi_reg23 |= 0x0100;
printf(" DP83840 specific setup, setting register 23 to %hX.\n",
}
whereami ("Done DP8340 special setup.");
if (options != 0) {
whereami ("set mdio_register.");
}
whereami ("started TX thingy (config, iasetup).");
/* Wait */;
/* Read the status register once to disgard stale data */
/* Check to see if the network cable is plugged in.
* This allows for faster failure if there is nothing
* we can do.
*/
printf("Valid link not established\n");
return 0;
}
return 1;
}
/*********************************************************************/
#ifdef DEBUG
/* Hexdump a number of bytes from memory... */
{
int i;
while (n > 0) {
for (i=0;i < ( (n>16)?16:n);i++)
printf ("\n");
n -= 16;
where += 16;
}
}
#endif
};
/* Cards with device ids 0x1030 to 0x103F, 0x2449, 0x2459 or 0x245D might need
* a workaround for hardware bug on 10 mbit half duplex (see linux driver eepro100.c)
* 2003/03/17 gbaum */
.type = NIC_DRIVER,
.name = "EEPRO100",
.probe = eepro100_probe,
.ids = eepro100_nics,
.class = 0
};