/*
*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 2015, Joyent, Inc.
*/
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/* Copyright (c) 1988 AT&T */
/* All Rights Reserved */
#include "dis_tables.h"
/* BEGIN CSTYLED */
/*
* Disassembly begins in dis_distable, which is equivalent to the One-byte
* Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
* decoding loops then traverse out through the other tables as necessary to
* decode a given instruction.
*
* The behavior of this file can be controlled by one of the following flags:
*
* DIS_TEXT Include text for disassembly
* DIS_MEM Include memory-size calculations
*
* Either or both of these can be defined.
*
* This file is not, and will never be, cstyled. If anything, the tables should
* be taken out another tab stop or two so nothing overlaps.
*/
/*
* These functions must be provided for the consumer to do disassembly.
*/
#ifdef DIS_TEXT
extern int strcmp(const char *, const char *);
#endif
/* field terminates - no pointer. */
/* Used to decode instructions. */
typedef struct instable {
#ifdef DIS_TEXT
#endif
#ifdef DIS_MEM
#endif
} instable_t;
/*
* Instruction formats.
*/
enum {
MRw,
IMlw,
IMw,
IR,
OA,
AO,
MS,
SM,
Mv,
Mw,
M, /* register or memory */
PREF,
R,
RA,
SEG,
MR,
RM,
IA,
MA,
SD,
AD,
SA,
D,
INM,
SO,
BD,
I,
P,
V,
U,
O, /* for call */
F, /* for 287 instructions */
/*
*/
};
/*
* VEX prefixes
*/
/*
** Register numbers for the i386
*/
#define EAX_REGNO 0
/*
* modes for immediate values
*/
#define MODE_NONE 0
/*
* The letters used in these macros are:
* IND - indirect to another to another table
* "T" - means to Terminate indirections (this is the final opcode)
* "S" - means "operand length suffix required"
* "Sa" - means AVX2 suffix (d/q) required
* "NS" - means "no suffix" which is the operand length suffix of the opcode
* "Z" - means instruction size arg required
* "u" - means the opcode is invalid in IA32 but valid in amd64
* "x" - means the opcode is invalid in amd64, but not IA32
* "y" - means the operand size is always 64 bits in 64 bit mode
* "vr" - means VEX instruction that operates on normal registers, not fpu
*/
#else
#endif
#ifdef DIS_TEXT
/*
* this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
*/
"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
"(%bx)",
"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
"(%bx)",
"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
"(%bx)",
};
/*
* This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
*/
"(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)",
"(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)"
};
"(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)",
"(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
};
/*
* This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
*/
"(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)",
"(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
};
"(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)",
"(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
};
/*
* decode for scale from SIB byte
*/
/*
* decode for scale from VSIB byte, note that we always include the scale factor
* to match gas.
*/
/*
* register decoding for normal references to registers (ie. not addressing)
*/
"%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
};
"%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
};
"%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
"%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
};
"%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
"%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
};
"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
};
"%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7",
"%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
};
"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
"%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
};
"%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
"%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
};
"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
};
"%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
"%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15"
};
"%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
"%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15"
};
"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
};
/*
* SIMD predicate suffixes
*/
"eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
};
/*0 1 2 3 4 5 6 7*/
/*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""},
/*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""},
/*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"}
};
#endif /* DIS_TEXT */
/*
* "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
*/
/*
* "decode table" for pause and clflush instructions
*/
/*
* Decode table for 0x0F00 opcodes
*/
};
/*
* Decode table for 0x0F01 opcodes
*/
/* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
};
/*
* Decode table for 0x0F18 opcodes -- SIMD prefetch
*/
/* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
};
/*
*/
/* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
};
/*
* Decode table for 0x0FBA opcodes
*/
};
/*
* Decode table for 0x0FC7 opcode (group 9)
*/
};
/*
* Decode table for 0x0FC7 opcode (group 9) mode 3
*/
};
/*
* Decode table for 0x0FC7 opcode with 0x66 prefix
*/
};
/*
* Decode table for 0x0FC7 opcode with 0xF3 prefix
*/
};
/*
* Decode table for 0x0FC8 opcode -- 486 bswap instruction
*
*bit pattern: 0000 1111 1100 1reg
*/
};
/*
* Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
*/
{
}, {
}, {
}, {
} };
/*
* Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
*/
};
/*
* SIMD instructions have been wedged into the existing IA32 instruction
* set through the use of prefixes. That is, while 0xf0 0x58 may be
* addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
* instruction - addss. At present, three prefixes have been coopted in
* this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
* following tables are used to provide the prefixed instruction names.
* The arrays are sparse, but they're fast.
*/
/*
* Decode table for SIMD instructions with the address size (0x66) prefix.
*/
/* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
/* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8),
/* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
/* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
/* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
/* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
/* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
/* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
/* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
/* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
/* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
/* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
/* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
/* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
};
/* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
/* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
/* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16),
/* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
/* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
/* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
/* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
/* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
/* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
/* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
/* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
/* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
/* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
/* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
/* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
/* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
/* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
/* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
/* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
/* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
/* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
/* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
/* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
/* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
/* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID,
};
/*
* Decode table for SIMD instructions with the repnz (0xf2) prefix.
*/
};
/* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
/* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
};
};
};
};
/*
* Decode table for SIMD instructions with the repz (0xf3) prefix.
*/
/* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
};
/* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID,
/* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4),
/* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16),
/* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4),
};
/*
* The following two tables are used to encode crc32 and movbe
* since they share the same opcodes.
*/
};
};
/*
* The following table is used to distinguish between adox and adcx which share
* the same opcodes.
*/
};
/* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
/* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
/* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
/* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16),
/* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
/* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
/* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
/* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16),
/* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
/* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
/* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
};
/* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
/* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
/* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
/* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
/* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
/* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
/* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
/* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
/* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
/* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
/* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
/* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
/* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
/* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
/* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
/* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
/* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
/* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
/* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
/* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
/* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
/* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
};
/* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
/* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
/* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
/* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
/* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
};
/* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
/* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
/* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
/* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
/* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
/* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
/* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
/* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
};
/*
* Decode table for 0x0F0D which uses the first byte of the mod_rm to
* indicate a sub-code.
*/
};
/*
* Decode table for 0x0F opcodes
*/
{
}, {
/* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
/* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
}, {
/* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
/* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
}, {
}, {
}, {
/* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
/* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16),
/* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
/* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16),
}, {
/* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
/* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
/* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
}, {
}, {
}, {
}, {
}, {
}, {
}, {
}, {
/* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8),
}, {
/* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8),
} };
{
}, {
/* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8),
/* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
}, {
/* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16),
}, {
}, {
}, {
/* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
/* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16),
/* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
/* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16),
}, {
}, {
}, {
}, {
}, {
}, {
}, {
}, {
}, {
}, {
} };
/*
* Decode table for 0x80 opcodes
*/
};
/*
* Decode table for 0x81 opcodes.
*/
};
/*
* Decode table for 0x82 opcodes.
*/
};
/*
* Decode table for 0x83 opcodes.
*/
};
/*
* Decode table for 0xC0 opcodes.
*/
};
/*
* Decode table for 0xD0 opcodes.
*/
};
/*
* Decode table for 0xC1 opcodes.
* 186 instruction set
*/
};
/*
* Decode table for 0xD1 opcodes.
*/
};
/*
* Decode table for 0xD2 opcodes.
*/
};
/*
* Decode table for 0xD3 opcodes.
*/
};
/*
* Decode table for 0xF6 opcodes.
*/
};
/*
* Decode table for 0xF7 opcodes.
*/
};
/*
* Decode table for 0xFE opcodes.
*/
};
/*
* Decode table for 0xFF opcodes.
*/
};
/* for 287 instructions, which are a mess to decode */
{
/* bit pattern: 1101 1xxx MODxx xR/M */
}, {
}, {
}, {
}, {
}, {
}, {
}, {
} };
{
/* bit pattern: 1101 1xxx 11xx xREG */
}, {
}, {
}, {
}, {
}, {
}, {
}, {
} };
{
/* bit pattern: 1101 1001 111x xxxx */
}, {
}, {
}, {
} };
/* bit pattern: 1101 1011 111x xxxx */
};
/* bit pattern: 1101 1011 11yy yxxx */
};
/* bit pattern: 1101 1010 11yy yxxx */
};
/*
* Main decode table for the op codes. The first two nibbles
* will be used as an index into the table. If there is a
* a need to further decode an instruction, the array to be
* referenced is indicated with the other two entries being
* empty.
*/
{
}, {
}, {
}, {
}, {
}, {
}, {
/* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
}, {
}, {
}, {
}, {
}, {
}, {
}, {
/* 287 instructions. Note that although the indirect field */
/* indicates opFP1n2 for further decoding, this is not necessarily */
/* the case since the opFP arrays are not partitioned according to key1 */
/* and key2. opFP1n2 is given only to indicate that we haven't */
/* finished decoding the instruction. */
}, {
}, {
} };
/* END CSTYLED */
/*
* common functions to decode and disassemble an x86 or amd64 instruction
*/
/*
* These are the individual fields of a REX prefix. Note that a REX
* prefix with none of these set is still needed to:
* - use the MOVSXD (sign extend 32 to 64 bits) instruction
* - access the %sil, %dil, %bpl, %spl registers
*/
/*
* These are the individual fields of a VEX prefix.
*/
/* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
/* VEX m-mmmm field, only used by three bytes prefix */
/* VEX pp field, providing equivalent functionality of a SIMD prefix */
/*
* Even in 64 bit mode, usually only 4 byte immediate operands are supported.
*/
/*
* Just a bunch of useful macros.
*/
/*
* The AVX2 gather instructions are a bit of a mess. While there's a pattern,
* there's not really a consistent scheme that we can use to know what the mode
* is supposed to be for a given type. Various instructions, like VPGATHERDD,
* always match the value of VEX_L. Other instructions like VPGATHERDQ, have
* some registers match VEX_L, but the VSIB is always XMM.
*
* The simplest way to deal with this is to just define a table based on the
* instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
* them.
*
* We further have to subdivide this based on the value of VEX_W and the value
* of VEX_L. The array is constructed to be indexed as:
* [opcode - 0x90][VEX_W][VEX_L].
*/
/* w = 0, 0x90 */
typedef struct dis_gather_regs {
{
/* op 0x90, W.0 */
{
},
/* op 0x90, W.1 */
{
}
},
{
/* op 0x91, W.0 */
{
},
/* op 0x91, W.1 */
{
}
},
{
/* op 0x92, W.0 */
{
},
/* op 0x92, W.1 */
{
}
},
{
/* op 0x93, W.0 */
{
},
/* op 0x93, W.1 */
{
}
}
};
/*
* Get the next byte and separate the op code into the high and low nibbles.
*/
static int
{
int byte;
/*
* x86 instructions have a maximum length of 15 bytes. Bail out if
* we try to read more.
*/
if (x->d86_len >= 15)
return (x->d86_error = 1);
if (x->d86_error)
return (1);
if (byte < 0)
return (x->d86_error = 1);
return (0);
}
/*
* Get and decode an SIB (scaled index base) byte
*/
static void
{
int byte;
if (x->d86_error)
return;
if (byte < 0) {
x->d86_error = 1;
return;
}
}
/*
* Get the byte following the op code and separate it into the
* mode, register, and r/m fields.
*/
static void
{
if (x->d86_got_modrm == 0) {
if (x->d86_rmindex == -1)
x->d86_rmindex = x->d86_len;
x->d86_got_modrm = 1;
}
}
/*
* Adjust register selection based on any REX prefix bits present.
*/
/*ARGSUSED*/
static void
{
if (rex_prefix & REX_B)
*reg += 8;
} else {
*reg += 8;
*r_m += 8;
}
}
/*
* Adjust register selection based on any VEX prefix bits present.
* Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
*/
/*ARGSUSED*/
static void
{
*reg += 8;
} else {
*reg += 8;
*r_m += 8;
}
}
/*
* Get an immediate operand of the given size, with sign extension.
*/
static void
{
int i;
int byte;
int valsize;
switch (wbit) {
case BYTE_OPND:
valsize = 1;
break;
case LONG_OPND:
if (x->d86_opnd_size == SIZE16)
valsize = 2;
else if (x->d86_opnd_size == SIZE32)
valsize = 4;
else
valsize = 8;
break;
case MM_OPND:
case XMM_OPND:
case YMM_OPND:
case SEG_OPND:
case CONTROL_OPND:
case DEBUG_OPND:
case TEST_OPND:
break;
case WORD_OPND:
valsize = 2;
break;
}
if (x->d86_error)
return;
for (i = 0; i < size; ++i) {
if (byte < 0) {
x->d86_error = 1;
return;
}
}
/* Do sign extension */
for (; i < sizeof (uint64_t); i++)
}
#ifdef DIS_TEXT
x->d86_imm_bytes += size;
#endif
}
/*
* Get an ip relative operand of the given size, with sign extension.
*/
static void
{
#ifdef DIS_TEXT
#endif
}
/*
* Check to see if there is a segment override prefix pending.
* If so, print it in the current 'operand' location and set
* the override flag back to false.
*/
/*ARGSUSED*/
static void
{
#ifdef DIS_TEXT
if (x->d86_seg_prefix) {
x->d86_seg_prefix, PFIXLEN);
}
#endif
x->d86_seg_prefix = NULL;
}
/*
* Process a single instruction Register or Memory operand.
*
* mode = addressing mode from ModRM byte
* r_m = r_m (or reg if mode == 3) field from ModRM byte
* wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
* o = index of operand that we are processing (0, 1 or 2)
*
* the value of reg or r_m must have already been adjusted for any REX prefix.
*/
/*ARGSUSED*/
static void
{
#ifdef DIS_TEXT
#endif
if (x->d86_error)
return;
/*
* first handle a simple register
*/
#ifdef DIS_TEXT
switch (wbit) {
case MM_OPND:
break;
case XMM_OPND:
break;
case YMM_OPND:
break;
case SEG_OPND:
break;
case CONTROL_OPND:
break;
case DEBUG_OPND:
break;
case TEST_OPND:
break;
case BYTE_OPND:
if (x->d86_rex_prefix == 0)
else
break;
case WORD_OPND:
break;
case LONG_OPND:
if (x->d86_opnd_size == SIZE16)
else if (x->d86_opnd_size == SIZE32)
else
break;
}
#endif /* DIS_TEXT */
return;
}
/*
* if symbolic representation, skip override prefix, if any
*/
/*
* Handle 16 bit memory references first, since they decode
* the mode values more simply.
* mode 1 is r_m + 8 bit displacement
* mode 2 is r_m + 16 bit displacement
* mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
*/
if (x->d86_addr_size == SIZE16) {
else if (mode == 1)
#ifdef DIS_TEXT
else if (mode == 0)
else
#endif
return;
}
/*
* 32 and 64 bit addressing modes are more complex since they
* can involve an SIB (scaled index and base) byte to decode.
*/
have_SIB = 1;
if (x->d86_error)
return;
if (x->d86_rex_prefix & REX_B)
base += 8;
if (x->d86_rex_prefix & REX_X)
index += 8;
} else {
}
/*
* Compute the displacement size and get its bytes
*/
dispsize = 0;
if (mode == 1)
dispsize = 1;
else if (mode == 2)
dispsize = 4;
dispsize = 4;
if (dispsize > 0) {
if (x->d86_error)
return;
}
#ifdef DIS_TEXT
if (dispsize > 0)
if (have_SIB == 0) {
if (mode == 0)
OPLEN);
else
OPLEN);
} else {
if (mode == 0) {
OPLEN);
if (r_m == 5) {
}
} else {
OPLEN);
}
}
} else {
char **regs;
char **bregs;
const char *const *sf;
else
if (x->d86_vsib != 0) {
bregs = (char **)dis_YMMREG;
else
bregs = (char **)dis_XMMREG;
} else {
}
/*
* print the base (if any)
*/
need_paren = 1;
}
} else {
need_paren = 1;
}
/*
* print the index (if any)
*/
} else
if (need_paren)
}
#endif
}
/*
* Operand sequence for standard instruction involving one register
* wbit indicates a byte(0) or opnd_size(1) operation
* vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
*/
}
/*
* Similar to above, but allows for the two operands to be of different
* classes (ie. wbit).
* wbit is for the r_m operand
* w2 is for the reg operand
*/
}
/*
* Similar, but for 2 operands plus an immediate.
* vbit indicates direction
* 0 for "opcode imm, r, r_m" or
* 1 for "opcode imm, r_m, r"
*/
}
/*
* Similar, but for 2 operands plus two immediates.
*/
}
/*
* 1 operands plus two immediates.
*/
}
/*
* Dissassemble a single x86 or amd64 instruction.
*
* Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
* for interpreting instructions.
*
* returns non-zero for bad opcode
*/
int
{
#ifdef DIS_TEXT
uint_t i;
#endif
#ifdef DIS_MEM
#else
#endif
/*
* legacy prefixes come in 5 flavors, you should have only one of each
*/
/*
* Intel VEX instruction encoding prefix and fields
*/
/* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
/*
* VEX prefix byte 1, includes vex.r, vex.x and vex.b
* (for 3 bytes prefix)
*/
/*
* For 32-bit mode, it should prefetch the next byte to
*/
#ifdef DIS_TEXT
/* Instruction name for BLS* family of instructions */
char *blsinstr;
#endif
x->d86_len = 0;
x->d86_rmindex = -1;
x->d86_error = 0;
#ifdef DIS_TEXT
x->d86_numopnds = 0;
x->d86_seg_prefix = NULL;
x->d86_mnem[0] = 0;
for (i = 0; i < 4; ++i) {
x->d86_opnd[i].d86_prefix[0] = 0;
x->d86_opnd[i].d86_value_size = 0;
}
#endif
x->d86_rex_prefix = 0;
x->d86_got_modrm = 0;
x->d86_memsize = 0;
x->d86_vsib = 0;
} else {
}
/*
* Get one opcode byte and check for zero padding that follows
* jump tables.
*/
goto error;
#ifdef DIS_TEXT
#endif
goto done;
}
/*
* Gather up legacy x86 prefix bytes.
*/
for (;;) {
switch (dp->it_adrmode) {
case PREFIX:
break;
case LOCK:
break;
case OVERRIDE:
#ifdef DIS_TEXT
#endif
goto error;
break;
case AM:
break;
case DM:
break;
}
if (which_prefix == NULL)
break;
goto error;
}
/*
* Handle amd64 mode PREFIX values.
* We might have a REX prefix (opcodes 0x40-0x4f)
*/
segment_prefix = 0;
if (opcode1 == 0x4) {
goto error;
} else if (opcode1 == 0xC &&
/* AVX instructions */
x->d86_rex_prefix = 0x40;
}
/* LDS, LES or AVX */
vex_prefetch = 1;
/* AVX */
x->d86_rex_prefix = 0x40;
}
}
if (vex_prefix == VEX_2bytes) {
if (!vex_prefetch) {
goto error;
}
/*
* The vex.x and vex.b bits are not defined in two bytes
* mode vex prefix, their default values are 1
*/
if (vex_R == 0)
x->d86_rex_prefix |= REX_R;
goto error;
switch (vex_p) {
case VEX_p_66:
dp = (instable_t *)
break;
case VEX_p_F3:
dp = (instable_t *)
break;
case VEX_p_F2:
dp = (instable_t *)
break;
default:
dp = (instable_t *)
}
} else if (vex_prefix == VEX_3bytes) {
if (!vex_prefetch) {
goto error;
}
if (vex_R == 0)
x->d86_rex_prefix |= REX_R;
if (vex_X == 0)
x->d86_rex_prefix |= REX_X;
if (vex_B == 0)
x->d86_rex_prefix |= REX_B;
goto error;
if (vex_W)
x->d86_rex_prefix |= REX_W;
/* Only these three vex_m values valid; others are reserved */
(vex_m != VEX_m_0F3A))
goto error;
goto error;
switch (vex_p) {
case VEX_p_66:
dp = (instable_t *)
} else if (vex_m == VEX_m_0F38) {
dp = (instable_t *)
} else if (vex_m == VEX_m_0F3A) {
dp = (instable_t *)
} else {
goto error;
}
break;
case VEX_p_F3:
dp = (instable_t *)
} else if (vex_m == VEX_m_0F38) {
dp = (instable_t *)
} else {
goto error;
}
break;
case VEX_p_F2:
dp = (instable_t *)
} else if (vex_m == VEX_m_0F3A) {
dp = (instable_t *)
} else if (vex_m == VEX_m_0F38) {
dp = (instable_t *)
} else {
goto error;
}
break;
default:
dp = (instable_t *)
}
}
if (vex_prefix) {
if (dp->it_vexwoxmm) {
} else {
if (vex_L)
else
}
}
/*
* Deal with selection of operand and address size now.
* Note that the REX.W bit being set causes opnd_size_prefix to be
* ignored.
*/
else if (opnd_size_prefix)
if (addr_size_prefix)
if (opnd_size_prefix)
if (addr_size_prefix)
} else {
if (opnd_size_prefix)
if (addr_size_prefix)
}
/*
* The pause instruction - a repz'd nop. This doesn't fit
* with any of the other prefix goop added for SSE, so we'll
* special-case it here.
*/
rep_prefix = 0;
}
/*
* Some 386 instructions have 2 bytes of opcode before the mod_r/m
* byte so we may need to perform a table indirection.
*/
goto error;
opcode_bytes = 2;
goto error;
opcode_bytes = 3;
opcode_bytes = 3;
goto error;
#ifdef DIS_TEXT
goto error;
#endif
switch (dp->it_adrmode) {
case XMMP_66r:
case XMMPRM_66r:
case XMM3PM_66r:
if (opnd_size_prefix == 0) {
goto error;
}
break;
case XMMP_66o:
if (opnd_size_prefix == 0) {
/* SSSE3 MMX instructions */
#ifdef DIS_MEM
#endif
}
break;
default:
goto error;
}
opcode_bytes = 3;
goto error;
/*
* Both crc32 and movbe have the same 3rd opcode
* byte of either 0xF0 or 0xF1, so we use another
* indirection to distinguish between the two.
*/
if (rep_prefix != 0xF2) {
/* It is movbe */
dp++;
}
}
/*
* The adx family of instructions (adcx and adox)
* continue the classic Intel tradition of abusing
* arbitrary prefixes without actually meaning the
* prefix bit. Therefore, if we find either the
* opnd_size_prefix or rep_prefix we end up zeroing it
* out after making our determination so as to ensure
* that we don't get confused and accidentally print
* repz prefixes and the like on these instructions.
*
* In addition, these instructions are actually much
* closer to AVX instructions in semantics. Importantly,
* they always default to having 32-bit operands.
* However, if the CPU is in 64-bit mode, then and only
* then, does it use REX.w promotes things to 64-bits
* and REX.r allows 64-bit mode to use register r8-r15.
*/
if (opnd_size_prefix == 0 &&
rep_prefix == 0xf3) {
/* It is adox */
dp++;
} else if (opnd_size_prefix != 0x66 &&
rep_prefix != 0) {
/* It isn't adcx */
goto error;
}
opnd_size_prefix = 0;
rep_prefix = 0;
if (rex_prefix & REX_W)
}
#ifdef DIS_TEXT
goto error;
#endif
switch (dp->it_adrmode) {
case ADX:
break;
case RM_66r:
case XMM_66r:
case XMMM_66r:
if (opnd_size_prefix == 0) {
goto error;
}
break;
case XMM_66o:
if (opnd_size_prefix == 0) {
/* SSSE3 MMX instructions */
#ifdef DIS_MEM
#endif
}
break;
case CRC32:
if (rep_prefix != 0xF2) {
goto error;
}
rep_prefix = 0;
break;
case MOVBE:
if (rep_prefix != 0x0) {
goto error;
}
break;
default:
goto error;
}
} else {
}
}
/*
* If still not at a TERM decode entry, then a ModRM byte
* exists and its fields further decode the instruction.
*/
x->d86_got_modrm = 0;
if (x->d86_error)
goto error;
/*
* decode 287 instructions (D8-DF) from opcodeN
*/
else if (mode == 0x3)
dp = (instable_t *)
else
dp = (instable_t *)
} else {
}
}
/*
* In amd64 bit mode, ARPL opcode is changed to MOVSXD
* (sign extend 32bit to 64 bit)
*/
/*
* at this point we should have a correct (or invalid) opcode
*/
goto error;
goto error;
/*
*/
switch (dp->it_adrmode) {
case MMO:
case MMOIMPL:
case MMO3P:
case MMOM3:
case MMOMS:
case MMOPM:
case MMOPRM:
case MMOS:
case XMMO:
case XMMOM:
case XMMOMS:
case XMMOPM:
case XMMOS:
case XMMOMX:
case XMMOX3:
case XMMOXMM:
/*
* This is horrible. Some SIMD instructions take the
* form 0x0F 0x?? ..., which is easily decoded using the
* existing tables. Other SIMD instructions use various
* prefix bytes to overload existing instructions. For
* Example, addps is F0, 58, whereas addss is F3 (repz),
* F0, 58. Presumably someone got a raise for this.
*
* If we see one of the instructions which can be
* modified in this way (if we've got one of the SIMDO*
* address modes), we'll check to see if the last prefix
* was a repz. If it was, we strip the prefix from the
* mnemonic, and we indirect using the dis_opSIMDrepz
* table.
*/
/*
* Calculate our offset in dis_op0F
*/
goto error;
sizeof (instable_t);
/*
* Rewrite if this instruction used one of the magic prefixes.
*/
if (rep_prefix) {
if (rep_prefix == 0xf2)
else
rep_prefix = 0;
} else if (opnd_size_prefix) {
opnd_size_prefix = 0;
}
break;
case MG9:
/*
* More horribleness: the group 9 (0xF0 0xC7) instructions are
* allowed an optional prefix of 0x66 or 0xF3. This is similar
* to the SIMD business described above, but with a different
* addressing mode (and an indirect table), so we deal with it
* separately (if similarly).
*
* Intel further complicated this with the release of Ivy Bridge
* where they overloaded these instructions based on the ModR/M
* bytes. The VMX instructions have a mode of 0 since they are
* memory instructions but rdrand instructions have a mode of
* 0b11 (REG_ONLY) because they only operate on registers. While
* there are different prefix formats, for now it is sufficient
* to use a single different table.
*/
/*
* Calculate our offset in dis_op0FC7 (the group 9 table)
*/
goto error;
sizeof (instable_t);
/*
* If we have a mode of 0b11 then we have to rewrite this.
*/
break;
}
/*
* Rewrite if this instruction used one of the magic prefixes.
*/
if (rep_prefix) {
if (rep_prefix == 0xf3)
else
goto error;
rep_prefix = 0;
} else if (opnd_size_prefix) {
opnd_size_prefix = 0;
}
break;
case MMOSH:
/*
* As with the "normal" SIMD instructions, the MMX
* shuffle instructions are overloaded. These
* instructions, however, are special in that they use
* an extra byte, and thus an extra table. As of this
* writing, they only use the opnd_size prefix.
*/
/*
* Calculate our offset in dis_op0F7123
*/
sizeof (dis_op0F7123))
goto error;
if (opnd_size_prefix) {
sizeof (instable_t);
opnd_size_prefix = 0;
}
break;
case MRw:
if (rep_prefix) {
if (rep_prefix == 0xf3) {
/*
* Calculate our offset in dis_op0F
*/
> sizeof (dis_op0F))
goto error;
sizeof (instable_t);
rep_prefix = 0;
} else {
goto error;
}
}
break;
}
/*
* In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
*/
#ifdef DIS_TEXT
/*
* At this point most instructions can format the opcode mnemonic
* including the prefixes.
*/
if (lock_prefix)
if (rep_prefix == 0xf2)
else if (rep_prefix == 0xf3)
goto error;
OPLEN);
/* It's a cmovx.yy. Replace the suffix x */
for (i = 5; i < OPLEN; i++) {
if (x->d86_mnem[i] == '.')
break;
}
/*
* To handle PINSRD and PEXTRD
*/
} else {
OPLEN);
}
}
}
#endif
/*
* Process operands based on the addressing modes.
*/
/*
* In vex mode the rex_prefix has no meaning
*/
if (!vex_prefix)
x->d86_rex_prefix = rex_prefix;
x->d86_opnd_size = opnd_size;
x->d86_addr_size = addr_size;
switch (dp->it_adrmode) {
/*
* into 64 bit register values
*/
case MOVSXZ:
#ifdef DIS_TEXT
if (rex_prefix == 0)
#endif
x->d86_opnd_size = SIZE64;
break;
/*
* movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
* movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
* wbit lives in 2nd byte, note that operands
* are different sized
*/
case MOVZ:
if (rex_prefix & REX_W) {
/* target register size = 64 bit */
}
break;
case CRC32:
if (rex_prefix & REX_W)
x->d86_opnd_size = opnd_size;
if (opnd_size_prefix)
break;
case MOVBE:
if (rex_prefix & REX_W)
x->d86_opnd_size = opnd_size;
if (opnd_size_prefix)
if (wbit) {
/* reg -> mem */
} else {
/* mem -> reg */
}
break;
/*
* imul instruction, with either 8-bit or longer immediate
* opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
*/
case IMUL:
break;
/* memory or register operand to register, with 'w' bit */
case MRw:
case ADX:
break;
/* register to memory or register operand, with 'w' bit */
/* arpl happens to fit here also because it is odd */
case RMw:
if (opcode_bytes == 2)
else
break;
/* xaddb instruction */
case XADDB:
wbit = 0;
break;
/* MMX register to memory or register operand */
case MMS:
case MMOS:
#ifdef DIS_TEXT
#else
#endif
break;
/* MMX register to memory */
case MMOMS:
goto error;
break;
/* Double shift. Has immediate operand specifying the shift. */
case DSHIFT:
break;
/*
* Double shift. With no immediate operand, specifies using %cl.
*/
case DSHIFTcl:
break;
/* immediate to memory or register operand */
case IMlw:
/*
* Have long immediate for opcode 0x81, but not 0x80 nor 0x83
*/
break;
/* immediate to memory or register operand with the */
/* 'w' bit present */
case IMw:
break;
/* immediate to register with register in low 3 bits */
/* of op code */
case IR:
/* w-bit here (with regs) is bit 3 */
break;
/* MMX immediate shift of register */
case MMSH:
case MMOSH:
goto mm_shift; /* in next case */
/* SIMD immediate shift of register */
case XMMSH:
break;
/* accumulator to memory operand */
case AO:
vbit = 1;
/*FALLTHROUGH*/
/* memory operand to accumulator */
case OA:
#ifdef DIS_TEXT
#endif
break;
/* segment register to memory or register operand */
case SM:
vbit = 1;
/*FALLTHROUGH*/
/* memory or register operand to segment register */
case MS:
break;
/*
* rotate or shift instructions, which may shift by 1 or
* consult the cl register, depending on the 'v' bit
*/
case Mv:
#ifdef DIS_TEXT
if (vbit) {
} else {
}
#endif
break;
/*
* immediate rotate or shift instructions
*/
case MvI:
break;
/* bit test instructions */
case MIb:
goto normal_imm_mem;
/* single memory or register operand with 'w' bit present */
case Mw:
break;
case SWAPGS_RDTSCP:
#ifdef DIS_TEXT
#endif
break;
#ifdef DIS_TEXT
#endif
break;
}
/*FALLTHROUGH*/
/* prefetch instruction - memory operand, but no memory acess */
case PREF:
/*FALLTHROUGH*/
/* single memory or register operand */
case M:
case MG9:
goto just_mem;
/* single memory or register byte operand */
case Mb:
goto just_mem;
case VMx:
if (mode == 3) {
#ifdef DIS_TEXT
char *vminstr;
switch (r_m) {
case 1:
vminstr = "vmcall";
break;
case 2:
vminstr = "vmlaunch";
break;
case 3:
vminstr = "vmresume";
break;
case 4:
vminstr = "vmxoff";
break;
default:
goto error;
}
#else
goto error;
#endif
break;
}
/*FALLTHROUGH*/
case SVM:
if (mode == 3) {
#if DIS_TEXT
char *vinstr;
switch (r_m) {
case 0:
vinstr = "vmrun";
break;
case 1:
vinstr = "vmmcall";
break;
case 2:
vinstr = "vmload";
break;
case 3:
vinstr = "vmsave";
break;
case 4:
vinstr = "stgi";
break;
case 5:
vinstr = "clgi";
break;
case 6:
vinstr = "skinit";
break;
case 7:
vinstr = "invlpga";
break;
}
#endif
break;
}
/*FALLTHROUGH*/
case MONITOR_MWAIT:
if (mode == 3) {
if (r_m == 0) {
#ifdef DIS_TEXT
#endif
break;
} else if (r_m == 1) {
#ifdef DIS_TEXT
#endif
break;
} else if (r_m == 2) {
#ifdef DIS_TEXT
#endif
break;
} else if (r_m == 3) {
#ifdef DIS_TEXT
#endif
break;
} else {
goto error;
}
}
/*FALLTHROUGH*/
case XGETBV_XSETBV:
if (mode == 3) {
if (r_m == 0) {
#ifdef DIS_TEXT
#endif
break;
} else if (r_m == 1) {
#ifdef DIS_TEXT
#endif
break;
} else {
goto error;
}
}
/*FALLTHROUGH*/
case MO:
/* Similar to M, but only memory (no direct registers) */
if (mode == 3)
goto error;
break;
/* move special register to register or reverse if vbit */
case SREG:
switch (opcode5) {
case 2:
vbit = 1;
/*FALLTHROUGH*/
case 0:
wbit = CONTROL_OPND;
break;
case 3:
vbit = 1;
/*FALLTHROUGH*/
case 1:
wbit = DEBUG_OPND;
break;
case 6:
vbit = 1;
/*FALLTHROUGH*/
case 4:
break;
}
break;
/*
* single register operand with register in the low 3
* bits of op code
*/
case R:
if (opcode_bytes == 2)
else
break;
/*
* register to accumulator with register in the low 3
* bits of op code, xchg instructions
*/
case RA:
break;
/*
* single segment register operand, with register in
* bits 3-4 of op code byte
*/
case SEG:
break;
/*
* single segment register operand, with register in
* bits 3-5 of op code
*/
case LSEG:
/* long seg reg from opcode */
break;
/* memory or register operand to register */
case MR:
if (vex_prefetch)
x->d86_got_modrm = 1;
break;
case RM:
case RM_66r:
break;
case MM:
case MMO:
#ifdef DIS_TEXT
#else
#endif
break;
case MMOIMPL:
#ifdef DIS_TEXT
#else
#endif
goto error;
mode = 0; /* change for memory access size... */
break;
case MMO3P:
goto xmm3p;
case XMM3P:
goto error;
1);
break;
case XMM3PM_66r:
1, 0);
break;
case MMOPRM:
goto xmmprm;
case XMMPRM:
case XMMPRM_66r:
break;
case MMOPM:
case MMOPM_66o:
goto xmmprm;
case MMOM3:
goto error;
break;
/* SIMD memory or xmm reg operand to xmm reg */
case XMM:
case XMM_66o:
case XMM_66r:
case XMMO:
case XMMXIMPL:
goto error;
#ifdef DIS_TEXT
/*
* movlps and movhlps share opcodes. They differ in the
* addressing modes allowed for their operands.
* movhps and movlhps behave similarly.
*/
}
#endif
mode = 0; /* change for memory access size... */
break;
/* SIMD xmm reg to memory or xmm reg */
case XMMS:
case XMMOS:
case XMMMS:
case XMMOMS:
#ifdef DIS_TEXT
goto error;
#endif
break;
/* SIMD memory to xmm reg */
case XMMM:
case XMMM_66r:
case XMMOM:
#ifdef DIS_TEXT
else
goto error;
}
#endif
break;
/* SIMD memory or r32 to xmm reg */
case XMM3MX:
break;
case XMM3MXS:
break;
/* SIMD memory or mm reg to xmm reg */
case XMMOMX:
/* SIMD mm to xmm */
case XMMMX:
break;
/* SIMD memory or xmm reg to mm reg */
case XMMXMM:
case XMMOXMM:
case XMMXM:
break;
/* SIMD memory or xmm reg to r32 */
case XMMXM3:
break;
/* SIMD xmm to r32 */
case XMMX3:
case XMMOX3:
goto error;
break;
case XMMP:
case XMMP_66r:
case XMMP_66o:
case XMMOPM:
1);
#ifdef DIS_TEXT
/*
* cmpps and cmpss vary their instruction name based
* on the value of imm8. Other XMMP instructions,
* such as shufps, require explicit specification of
* the predicate.
*/
if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *)))
goto error;
OPLEN);
OPLEN);
x->d86_numopnds = 2;
}
#endif
break;
case XMMX2I:
1);
break;
case XMM2I:
break;
/* immediate operand to accumulator */
case IA:
break;
/* memory or register operand to accumulator */
case MA:
break;
/* si register to di register used to reference memory */
case SD:
#ifdef DIS_TEXT
dtrace_check_override(x, 0);
x->d86_numopnds = 2;
OPLEN);
OPLEN);
OPLEN);
OPLEN);
} else {
OPLEN);
OPLEN);
}
#endif
break;
/* accumulator to di register */
case AD:
#ifdef DIS_TEXT
dtrace_check_override(x, 1);
x->d86_numopnds = 2;
OPLEN);
OPLEN);
else
OPLEN);
#endif
break;
/* si register to accumulator */
case SA:
#ifdef DIS_TEXT
dtrace_check_override(x, 0);
x->d86_numopnds = 2;
OPLEN);
OPLEN);
else
OPLEN);
#endif
break;
/*
* single operand, a 16/32 bit displacement
*/
case D:
break;
case INM:
#ifdef DIS_TEXT
#endif
break;
/*
* for long jumps and long calls -- a new code segment
* register and an offset in IP -- stored in object
* code in reverse order. Note - not valid in amd64
*/
case SO:
dtrace_check_override(x, 1);
#ifdef DIS_TEXT
#endif
/* will now get segment operand */
break;
/*
* added to current EIP in 'compofff'
*/
case BD:
break;
/* single 32/16 bit immediate operand */
case I:
break;
/* single 8 bit immediate operand */
case Ib:
break;
case ENTER:
switch (opnd_size) {
case SIZE64:
break;
case SIZE32:
break;
case SIZE16:
break;
}
break;
/* 16-bit immediate operand */
case RET:
break;
/* single 8 bit port operand */
case P:
dtrace_check_override(x, 0);
break;
/* single operand, dx register (variable port instruction) */
case V:
x->d86_numopnds = 1;
dtrace_check_override(x, 0);
#ifdef DIS_TEXT
#endif
break;
/*
* The int instruction, which has two forms:
* int 3 (breakpoint) or
* int n, where n is indicated in the subsequent
* byte (format Ib). The int 3 instruction (opcode 0xCC),
* where, although the 3 looks like an operand,
* it is implied by the opcode. It must be converted
* to the correct base and output.
*/
case INT3:
#ifdef DIS_TEXT
x->d86_numopnds = 1;
#endif
break;
/* single 8 bit immediate operand */
case INTx:
break;
/* an unused byte must be discarded */
case U:
if (x->d86_get_byte(x->d86_data) < 0)
goto error;
x->d86_len++;
break;
case CBW:
#ifdef DIS_TEXT
else
#endif
break;
case CWD:
#ifdef DIS_TEXT
else
#endif
break;
case XMMSFNC:
/*
* sfence is sfence if mode is REG_ONLY. If mode isn't
* REG_ONLY, mnemonic should be 'clflush'.
*/
/* sfence doesn't take operands */
#ifdef DIS_TEXT
} else {
}
#else
}
#endif
break;
/*
* no disassembly, the mnemonic was all there was so go on
*/
case NORM:
goto error;
/*FALLTHROUGH*/
case IMPLMEM:
break;
case XMMFENCE:
/*
* XRSTOR and LFENCE share the same opcode but differ in mode
*/
/*
* Only the following exact byte sequences are allowed:
*
* 0f ae e8 lfence
* 0f ae f0 mfence
*/
goto error;
} else {
#ifdef DIS_TEXT
#endif
}
break;
/* float reg */
case F:
#ifdef DIS_TEXT
x->d86_numopnds = 1;
#endif
break;
/* float reg to float reg, with ret bit present */
case FF:
/*FALLTHROUGH*/
case FFC: /* case for vbit always = 0 */
#ifdef DIS_TEXT
x->d86_numopnds = 2;
#endif
break;
/* AVX instructions */
case VEX_MO:
x->d86_numopnds = 1;
#ifdef DIS_TEXT
#endif
break;
case VEX_RMrX:
case FMA:
x->d86_numopnds = 3;
/*
* In classic Intel fashion, the opcodes for all of the FMA
* instructions all have two possible mnemonics which vary by
* one letter, which is selected based on the value of the wbit.
* When wbit is one, they have the 'd' suffix and when 'wbit' is
* 0, they have the 's' suffix. Otherwise, the FMA instructions
* are all a standard VEX_RMrX.
*/
#ifdef DIS_TEXT
}
}
#endif
/* vmovsd <m64>, <xmm> */
/* or vmovss <m64>, <xmm> */
x->d86_numopnds = 2;
goto L_VEX_MX;
}
}
/*
* VEX prefix uses the 1's complement form to encode the
*/
/*
* vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
* <xmm>, <xmm>
*/
}
#ifdef DIS_TEXT
}
#endif
break;
case VEX_VRMrX:
x->d86_numopnds = 3;
/*
* VEX prefix uses the 1's complement form to encode the
*/
break;
case VEX_SbVM:
x->d86_numopnds = 3;
x->d86_vsib = 1;
/*
* All instructions that use VSIB are currently a mess. See the
* comment around the dis_gather_regs_t structure definition.
*/
#ifdef DIS_TEXT
#endif
/*
* VEX prefix uses the 1's complement form to encode the
*/
0);
break;
case VEX_RRX:
x->d86_numopnds = 3;
/* vmovsd <xmm>, <m64> */
/* or vmovss <xmm>, <m64> */
x->d86_numopnds = 2;
goto L_VEX_RM;
}
}
break;
case VEX_RMRX:
x->d86_numopnds = 4;
/* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
#ifdef DIS_TEXT
if (vex_W)
#endif
} else {
}
/* one byte immediate number */
/* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
#ifdef DIS_TEXT
#endif
#ifdef DIS_TEXT
if (vex_L)
else
#endif
}
break;
case VEX_MX:
x->d86_numopnds = 2;
/* vcvtpd2dq <ymm>, <xmm> */
/* or vcvtpd2ps <ymm>, <xmm> */
/* or vcvttpd2dq <ymm>, <xmm> */
/* vcvtdq2pd <xmm>, <ymm> */
/* or vcvtps2pd <xmm>, <ymm> */
/* or vcvtph2ps <xmm>, <ymm> */
/* or vbroadcasts* <xmm>, <ymm> */
#ifdef DIS_TEXT
if (vex_W)
#endif
} else {
}
break;
case VEX_MXI:
x->d86_numopnds = 3;
/* one byte immediate number */
break;
case VEX_XXI:
x->d86_numopnds = 3;
#ifdef DIS_TEXT
OPLEN);
#endif
/* one byte immediate number */
break;
case VEX_MR:
/* vpextrw <imm8>, <xmm>, <reg> */
x->d86_numopnds = 2;
vbit = 2;
} else {
x->d86_numopnds = 2;
vbit = 1;
}
if (vbit == 2)
break;
case VEX_RRI:
x->d86_numopnds = 2;
break;
case VEX_RX:
/* vextractf128 || vcvtps2ph */
x->d86_numopnds = 3;
/* one byte immediate number */
break;
}
x->d86_numopnds = 2;
break;
case VEX_RR:
x->d86_numopnds = 2;
#ifdef DIS_TEXT
if (vex_W)
#endif
} else
break;
case VEX_RRi:
x->d86_numopnds = 3;
#ifdef DIS_TEXT
if (vex_W)
}
#endif
/* one byte immediate number */
break;
case VEX_RIM:
x->d86_numopnds = 3;
/* one byte immediate number */
break;
case VEX_RM:
x->d86_numopnds = 3;
/* one byte immediate number */
break;
}
x->d86_numopnds = 2;
vbit = 1;
break;
case VEX_RRM:
x->d86_numopnds = 3;
break;
case VEX_RMX:
x->d86_numopnds = 3;
break;
case VEX_NONE:
#ifdef DIS_TEXT
if (vex_L)
#endif
break;
case BLS: {
/*
* The BLS instructions are VEX instructions that are based on
* VEX.0F38.F3; however, they are considered special group 17
* and like everything else, they use the bits in 3-5 of the
* MOD R/M to determine the sub instruction. Unlike many others
* like the VMX instructions, these are valid both for memory
* and register forms.
*/
switch (reg) {
case 1:
#ifdef DIS_TEXT
blsinstr = "blsr";
#endif
break;
case 2:
#ifdef DIS_TEXT
blsinstr = "blsmsk";
#endif
break;
case 3:
#ifdef DIS_TEXT
blsinstr = "blsi";
#endif
break;
default:
goto error;
}
x->d86_numopnds = 2;
#ifdef DIS_TEXT
#endif
break;
}
/* an invalid op code */
case AM:
case DM:
case OVERRIDE:
case PREFIX:
case UNKNOWN:
default:
goto error;
} /* end switch */
if (x->d86_error)
goto error;
done:
#ifdef DIS_MEM
/*
* compute the size of any memory accessed by the instruction
*/
if (x->d86_memsize != 0) {
return (0);
} else if (dp->it_stackop) {
switch (opnd_size) {
case SIZE16:
x->d86_memsize = 2;
break;
case SIZE32:
x->d86_memsize = 4;
break;
case SIZE64:
x->d86_memsize = 8;
break;
}
x->d86_memsize = 0;
/*
* In 64 bit mode descriptor table entries
*/
x->d86_memsize = 10;
x->d86_memsize = 8;
else
} else if (wbit == 0) {
x->d86_memsize = 1;
x->d86_memsize = 8;
x->d86_memsize = 4;
else
x->d86_memsize = 2;
x->d86_memsize = 4;
} else {
x->d86_memsize = 8;
}
#endif
return (0);
#ifdef DIS_TEXT
#endif
return (1);
}
#ifdef DIS_TEXT
/*
* Some instructions should have immediate operands printed
* as unsigned integers. We compare against this table.
*/
static char *unsigned_ops[] = {
"or", "and", "xor", "test", "in", "out", "lcall", "ljmp",
"rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl",
0
};
static int
{
char *where;
int i;
int is_unsigned = 0;
/*
* Work back to start of last mnemonic, since we may have
* prefixes on some opcodes.
*/
--where;
if (*where == ' ')
++where;
for (i = 0; unsigned_ops[i]; ++i) {
strlen(unsigned_ops[i])))
continue;
is_unsigned = 1;
break;
}
return (is_unsigned);
}
/*
* Print a numeric immediate into end of buf, maximum length buflen.
* The immediate may be an address or a displacement. Mask is set
* for address size. If the immediate is a "small negative", or
* if it's a negative displacement of any magnitude, print as -<absval>.
* Respect the "octal" flag. "Small negative" is defined as "in the
* interval [NEG_LIMIT, 0)".
*
* Also, "isunsigned_op()" instructions never print negatives.
*
* Return whether we decided to print a negative value or not.
*/
static int
{
int curlen;
return (1);
} else {
else
return (0);
}
}
static int
{
switch (size) {
case 1: return (0);
case 2: return (1);
case 4: return (2);
case 8: return (3);
}
return (0);
}
/* ARGSUSED */
void
{
int curlen;
int i;
{0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL};
save_usv = 0;
/*
* For PC-relative jumps, the pc is really the next pc after executing
* this instruction, so increment it appropriately.
*/
for (i = 0; i < dis->d86_numopnds; i++) {
if (i != 0)
/*
* sv is for the signed, possibly-truncated immediate or
* displacement; usv retains the original size and
* unsignedness for symbol lookup.
*/
/*
* About masks: for immediates that represent
* addresses, the appropriate display size is
* the effective address size of the instruction.
* This includes MODE_OFFSET, MODE_IPREL, and
* MODE_RIPREL. Immediates that are simply
* immediate values should display in the operand's
* size, however, since they don't represent addresses.
*/
/* d86_addr_size is SIZEnn, which is log2(real size) */
/* d86_value_size and d86_imm_bytes are in bytes */
case MODE_NONE:
break;
case MODE_SIGNED:
case MODE_IMPLIED:
case MODE_OFFSET:
if (dis->d86_seg_prefix)
buflen);
}
/*
* We printed a negative value for an
* immediate that wasn't a
* displacement. Note that fact so we can
* print the positive value as an
* annotation.
*/
}
break;
case MODE_IPREL:
case MODE_RIPREL:
switch (mode) {
case SIZE16:
break;
case SIZE32:
break;
}
break;
}
}
/*
* The symbol lookups may result in false positives,
* particularly on object files, where small numbers may match
* the 0-relative non-relocated addresses of symbols.
*/
if (tgt != 0) {
}
/*
* If we printed a negative immediate above, print the
* positive in case our heuristic was unhelpful
*/
if (save_usv) {
}
}
if (reltgt != 0) {
/* Print symbol or effective address for reltgt */
}
}
#endif /* DIS_TEXT */