/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* A faulty Schizo hostbridge may cause:
*
* - bca: bad safari command from PCI block A.
* - bcb: bad safari command from PCI block B.
* - ciq-to: coherent input queue timeout.
* - lpq-to: local PIO queue timeout.
* - sfpq-to: safari foreign PIO queue timeout.
* - ufpq-to: UPA foreign PIO queue timeout.
* - ape: address parity error.
* - pue: PIO uncorrectable error, bad reader.
* - s-pue: secondary PIO UE, bad reader.
* - ecc: multiple PIO CEs.
* - to: safari bus timeout.
* - bus: safari bus error.
* - dstat: errant dstat on incoming data.
*
* The to, bus and dstat errors can cause a target abort to be sent onto the
* pci bus in response to a dma request. We represent this using a device-ta
* error to propagate into the generic pci.esc rules.
*/
/*
* An upset schizo may cause:
*
* - pce: PIO correctable error.
*/
/*
* A faulty xcal CPU[0] may cause:
*
* - cpu0-par: parity error on the unidirectional signals.
* - cpu0-bidi: parity error on the bi-directional signals.
*/
/*
* A faulty xcal CPU[1] may cause:
*
* - cpu1-par: parity error on the unidirectional signals.
* - cpu1-bidi: parity error on the bidirectional signals.
*/
/*
* A faulty CPU may cause:
*
* - to: safari bus timeout.
* - bus: safari bus error.
* - dstat: incorrect dstat sent to hostbridge.
* - ssm-dis: ssm command sent to hostbridge when not enabled.
* - ape: safari address parity error.
* - pue: PIO uncorrectable error.
* - ecc: multiple PIO CEs.
*/
/*
* A faulty host bus may cause:
*
* - ape: address parity error.
* - cpu0-par: parity error on the unidirectional signals.
* - cpu0-bidi: parity error on the bidirectional signals.
* - cpu1-par: parity error on the unidirectional signals.
* - cpu1-bidi: parity error on the bidirectional signals.
* - pue: PIO uncorrectable error.
* - s-pue: secondary PIO UE.
* - ecc: multiple PIO CEs.
*/
/*
*
* - um: safari unmapped address error.
* - mmu: a iommu translation error.
*/
/*
* A faulty PCI bus may cause:
*
* - bu: PCI bus unusable error.
* - s-bu: secondary PCI bus unusable error.
*/
/*
* A faulty PCI device may cause:
*
* - sbh: a streaming byte hole error.
* - rl: it to exceed the number retriesfor a transaction.
* - tto: it to not assert trdy# within the alloted timeout.
*
* For rl and tto, there may be a target- ereport on a child device. For rl,
* there may also be an associated dto - the retry-to-d error propagates into
* the pci.esc rules to handle this.
*/
/*
* Need to add the following schizo specific propagations to complete the PCI
* fault tree. These are to allow propagations to secondary errors and cpu
* bus errors, and to represent the way the chip can raise both rserr and sserr
* on detection of SERR#
*/
/*
* Upset used to hide ereports that can not be currently diagnosed.
*
* The drue error can cause a target abort to be sent onto the
* pci bus in response to a dma request. We represent this using a device-ta
* error to propagate into the generic pci.esc rules.
*/