/*-
* Copyright (c) 1991 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
* $FreeBSD$
*/
#ifndef _MACHINE_SPECIALREG_H_
#define _MACHINE_SPECIALREG_H_
/*
* Bits in 386 special registers:
*/
/*
* Bits in 486 special registers:
*/
all modes) */
/*
* Bits in PPro special registers
*/
/*
* Bits in AMD64 special registers. EFER is 64 bits wide.
*/
/*
* Intel Extended Features registers
*/
#define XFEATURE_AVX \
#define XFEATURE_AVX512 \
#define XFEATURE_MPX \
/*
* CPUID instruction features register
*/
/*
* Important bits in the Thermal and Power Management flags
* CPUID.6 EAX and ECX.
*/
/*
* Important bits in the AMD extended cpuid flags
*/
/*
* CPUID instruction 1 eax info
*/
#ifdef __i386__
#else
#endif
/*
* CPUID instruction 1 ebx info
*/
/*
* CPUID instruction 5 info
*/
/*
* MWAIT cpu power states. Lower 4 bits are sub-states.
*/
/*
* MWAIT extensions.
*/
/* Interrupt breaks MWAIT even when masked. */
/*
* CPUID instruction 6 ecx info
*/
/*
* CPUID instruction 0xb ebx info.
*/
#define CPUID_TYPE_INVAL 0
/*
* CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
*/
/*
* AMD extended function 8000_0007h edx info
*/
/*
* AMD extended function 8000_0008h ecx info
*/
/*
* CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
*/
/*
* CPUID manufacturers identifiers
*/
/*
* Model-specific registers for the i386 family
*/
/*
* VMX MSRs
*/
/*
* X2APIC MSRs
*/
/*
* Constants related to MSR's.
*/
/* MSR_IA32_FEATURE_CONTROL related */
/* MSR IA32_MISC_ENABLE */
/*
* PAT modes.
*/
/*
* Constants related to MTRRs
*/
/*
* Cyrix configuration registers, accessible as IO ports.
*/
non-cacheable */
state */
assoc */
hold state. */
/* Performance Control Register (5x86 only). */
serialize pipe. */
/* Device Identification Registers */
/*
* Machine Check register constants.
*/
/*
* The following four 3-byte registers control the non-cacheable regions.
* These registers must be written as three separate bytes.
*
* NCRx+0: A31-A24 of starting address
* NCRx+1: A23-A16 of starting address
* NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
*
* The non-cacheable region's starting address must be aligned to the
* size indicated by the NCR_SIZE_xx field.
*/
#define NCR_SIZE_0K 0
/*
* The address region registers are used to specify the location and
* size for the eight address regions.
*
* ARRx + 0: A31-A24 of start address
* ARRx + 1: A23-A16 of start address
* ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
*/
#define ARR_SIZE_0K 0
/*
* The region control registers specify the attributes associated with
* the ARRx addres regions.
*/
/* AMD Write Allocate Top-Of-Memory and Control Register */
/* AMD64 MSR's */
/* MSR_VM_CR related */
/* VIA ACE crypto featureset: for via_feature_rng */
/* VIA ACE crypto featureset: for via_feature_xcrypt */
/* Centaur Extended Feature flags */
/* VIA ACE xcrypt-* instruction context control options */
#endif /* !_MACHINE_SPECIALREG_H_ */