/*-
* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
/*
* PCIM_xxx: mask to locate subfield in register
* PCIR_xxx: config register offset
* PCIC_xxx: device class
* PCIS_xxx: device subclass
* PCIP_xxx: device programming interface
* PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
* PCID_xxx: device ID
* PCIY_xxx: capability identification number
* PCIZ_xxx: extended capability identification number
*/
/* some PCI bus constants */
#define PCIE_ARI_SLOTMAX 0
#define PCI_RID_FUNC_SHIFT 0
/* PCI config header registers for all devices */
/* Capability Register Offsets */
/* Capability Identification Numbers */
/* Extended Capability Register Fields */
/* Extended Capability Identification Numbers */
/* config registers for header type 0 devices */
#define PCIM_BAR_MEM_SPACE 0
#define PCIM_BAR_MEM_32 0
#define PCIM_CIS_ASI_CONFIG 0
/* config registers for header type 1 (PCI-to-PCI bridge) devices */
/* config registers for header type 2 (CardBus) devices */
#define PCIR_MAX_BAR_2 0
/* PCI device class, subclass and programming interface definitions */
/* Bridge Control Values. */
/* PCI power manangement */
/* VPD capability registers */
/* PCI Message Signalled Interrupts (MSI) */
/* PCI-X definitions */
/* For header type 0 devices */
/* For header type 1 devices (PCI-X bridges) */
/* HT (HyperTransport) Capability definitions */
/* HT MSI Mapping Capability definitions. */
/* PCI Vendor capability definitions */
/* PCI EHCI Debug Port definitions */
/* PCI-PCI Bridge Subvendor definitions */
/* PCI Express definitions */
/* MSI-X definitions */
#define PCIM_MSIX_BIR_BAR_10 0
/* PCI Advanced Features definitions */
/* Advanced Error Reporting */
/* Virtual Channel definitions */
/* Serial Number definitions */
/* SR-IOV definitions */