Searched refs:rcond (Results 1 - 3 of 3) sorted by relevance

/openjdk7/hotspot/agent/src/share/classes/sun/jvm/hotspot/asm/sparc/
H A DV9RegisterBranchDecoder.java45 abstract String getRegisterConditionName(int rcond); argument
49 int rcond = (BRANCH_RCOND_MASK & instruction) >>> BRANCH_RCOND_START_BIT;
50 if (rcond == BRANCH_RCOND_RESERVED1 || rcond == BRANCH_RCOND_RESERVED2)
57 String name = getRegisterConditionName(rcond);
58 return v9factory.newV9RegisterBranchInstruction(name, addr, annuled, rcond, rs1, predictTaken);
/openjdk7/langtools/src/share/classes/com/sun/tools/javac/jvm/
H A DGen.java1932 CondItem rcond = genCond(tree.rhs, CRT_FLOW_TARGET);
1934 makeCondItem(rcond.opcode,
1935 rcond.trueJumps,
1937 rcond.falseJumps));
1946 CondItem rcond = genCond(tree.rhs, CRT_FLOW_TARGET);
1948 makeCondItem(rcond.opcode,
1949 Code.mergeChains(trueJumps, rcond.trueJumps),
1950 rcond.falseJumps);
/openjdk7/hotspot/src/cpu/sparc/vm/
H A Dassembler_sparc.hpp973 static int rcond( RCondition x) { return u_field(x, 12, 10); } function in class:Assembler
1538 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
1547 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
1548 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }

Completed in 145 milliseconds