Searched refs:msiq_id (Results 1 - 13 of 13) sorted by relevance

/illumos-gate/usr/src/uts/sun4v/io/px/
H A Dpx_lib4v.h145 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id,
147 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id,
149 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
151 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
153 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
155 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
157 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
159 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
161 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
168 msiqid_t *msiq_id);
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H A Dpx_hcall.s84 hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra,
90 hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p,
96 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
102 hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
108 hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
114 hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
120 hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
126 hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
132 hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
139 msiqid_t *msiq_id)
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H A Dpx_lib4v.c780 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, argument
785 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n",
786 dip, msiq_id);
789 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) {
803 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, argument
808 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n",
809 dip, msiq_id);
812 msiq_id, msiq_valid_state)) != H_EOK) {
826 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, argument
831 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id
846 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, pci_msiq_state_t *msiq_state) argument
869 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, pci_msiq_state_t msiq_state) argument
889 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, msiqhead_t *msiq_head_p) argument
914 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, msiqhead_t msiq_head) argument
934 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, msiqtail_t *msiq_tail_p) argument
1003 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, msiqid_t *msiq_id) argument
1026 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, msiqid_t msiq_id, msi_type_t msitype) argument
1136 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, msiqid_t *msiq_id) argument
1159 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, msiqid_t msiq_id) argument
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/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_msiq.c85 msiq_state_p->msiq_p[i].msiq_id =
90 msiq_state_p->msiq_p[i].msiq_id));
134 msiq_state_p->msiq_p[i].msiq_id,
176 msiq_state_p->msiq_p[first_msiq_id].msiq_id;
181 "px_msiq_alloc: msiq_id 0x%x\n", *msiq_id_p);
203 *msiq_id_p = msiq_state_p->msiq_p[i].msiq_id;
208 *msiq_id_p = msiq_state_p->msiq_p[i].msiq_id;
216 "px_msiq_alloc: msiq_id 0x%x\n", *msiq_id_p);
258 *msiq_id_p = msiq_state_p->msiq_p[i].msiq_id;
264 free_msiq_id = msiq_state_p->msiq_p[i].msiq_id;
299 px_msiq_free(px_t *px_p, msiqid_t msiq_id) argument
359 px_msiqid_to_devino(px_t *px_p, msiqid_t msiq_id) argument
380 msiqid_t msiq_id; local
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H A Dpx_lib.h104 extern int px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id,
106 extern int px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id,
108 extern int px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id,
110 extern int px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id,
112 extern int px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id,
114 extern int px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id,
116 extern int px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id,
118 extern int px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id,
129 msiqid_t *msiq_id);
131 msiqid_t msiq_id, msi_type_
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H A Dpx_msiq.h37 msiqid_t msiq_id; /* MSIQ ID */ member in struct:px_msiq
92 extern int px_msiq_free(px_t *px_p, msiqid_t msiq_id);
95 extern devino_t px_msiqid_to_devino(px_t *px_p, msiqid_t msiq_id);
H A Dpx_intr.h50 msgcode_t msg_code, msiqid_t msiq_id);
H A Dpx_intr.c263 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x "
264 "ih_size=%x ih_lst=%x\n", msiq_p->msiq_id, ino_p->ino_ino,
279 px_lib_msiq_gettail(dip, msiq_p->msiq_id, &curr_tail_index);
450 px_lib_msiq_sethead(dip, msiq_p->msiq_id, msiq_p->msiq_new_head_index);
558 msiqid_t msiq_id; local
651 msiq_rec_type, msi_num, -1, &msiq_id)) != DDI_SUCCESS) {
657 DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id);
660 msiq_id, msi_type)) != DDI_SUCCESS) {
662 hdlp, msiq_rec_type, msi_num, msiq_id);
669 hdlp, msiq_rec_type, msi_num, msiq_id);
1300 px_rem_msiq_intr(dev_info_t *dip, dev_info_t *rdip, ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, msgcode_t msg_code, msiqid_t msiq_id) argument
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H A Dpx_tools.c134 msiqid_t msiq_id; local
150 &msiq_id) != DDI_SUCCESS)
153 iget->ino = px_msiqid_to_devino(px_p, msiq_id);
255 msiqid_t msiq_id; local
310 &msiq_id) != DDI_SUCCESS)
313 iset.ino = px_msiqid_to_devino(px_p, msiq_id);
355 (void) px_lib_msi_getmsiq(dip, iset.msi, &msiq_id);
356 iset.ino = px_msiqid_to_devino(px_p, msiq_id);
H A Dpx_ib.c928 msiqid_t msiq_id, old_msiq_id; local
997 msiq_rec_type, msi_num, cpu_id, &msiq_id)) != DDI_SUCCESS) {
1006 msiq_id, msi_type)) != DDI_SUCCESS) {
1010 hdlp, msiq_rec_type, msi_num, msiq_id);
1016 px_msiqid_to_devino(px_p, msiq_id), hdlp->ih_pri,
1021 hdlp, msiq_rec_type, msi_num, msiq_id);
1045 ino_p = px_ib_locate_ino(ib_p, px_msiqid_to_devino(px_p, msiq_id));
1052 hdlp, msiq_rec_type, msi_num, msiq_id);
/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.h340 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
342 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
344 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
346 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
348 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
350 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
352 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
361 msiqid_t *msiq_id);
363 msiqid_t msiq_id);
377 msiqid_t *msiq_id);
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H A Dpx_lib4u.c817 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, argument
824 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n",
825 dip, msiq_id);
829 (msiq_id * msiq_size));
841 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, argument
846 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n",
847 dip, msiq_id);
850 msiq_id, msiq_valid_state)) != H_EOK) {
864 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, argument
869 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id
884 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, pci_msiq_state_t *msiq_state) argument
907 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, pci_msiq_state_t msiq_state) argument
927 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, msiqhead_t *msiq_head) argument
950 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, msiqhead_t msiq_head) argument
970 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, msiqtail_t *msiq_tail) argument
1095 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, msiqid_t *msiq_id) argument
1118 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, msiqid_t msiq_id, msi_type_t msitype) argument
1227 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, msiqid_t *msiq_id) argument
1250 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, msiqid_t msiq_id) argument
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H A Dpx_hlib.c2265 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, argument
2272 msiq_id, ENTRIES_STATE);
2291 hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, argument
2299 msiq_id, ENTRIES_DIS);
2303 msiq_id, ENTRIES_EN);
2314 hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, argument
2321 msiq_id, ENTRIES_STATE);
2339 hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, argument
2346 msiq_id, ENTRIES_STATE);
2356 msiq_id, ENTRIES_ENOVER
2375 hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, msiqhead_t *msiq_head) argument
2385 hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, msiqhead_t msiq_head) argument
2395 hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, msiqtail_t *msiq_tail) argument
2426 hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, msiqid_t *msiq_id) argument
2436 hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, msiqid_t msiq_id) argument
2511 hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, msiqid_t *msiq_id) argument
2543 hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, msiqid_t msiq_id) argument
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