Searched refs:NXGE_REG_RD64 (Results 1 - 19 of 19) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_espc.c87 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), &val);
100 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), &val);
119 NXGE_REG_RD64(handle, ESPC_MAC_ADDR_0, &mac0.value);
125 NXGE_REG_RD64(handle, ESPC_MAC_ADDR_1, &mac1.value);
137 NXGE_REG_RD64(handle, ESPC_NUM_PORTS_MACS, &val);
149 NXGE_REG_RD64(handle, ESPC_NUM_PORTS_MACS, &val);
164 NXGE_REG_RD64(handle, ESPC_MOD_STR_LEN, &val);
181 NXGE_REG_RD64(handle, ESPC_MOD_STR(j), &val);
200 NXGE_REG_RD64(handle, ESPC_BD_MOD_STR_LEN, &val);
218 NXGE_REG_RD64(handl
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H A Dnpi_vir.c121 NXGE_REG_RD64(handle, pio_offset[i], &value);
130 NXGE_REG_RD64(handle, fzc_pio_offset[i], &value);
156 NXGE_REG_RD64(handle, offset, &value);
185 NXGE_REG_RD64(handle, offset, &value);
214 NXGE_REG_RD64(handle, offset,
228 NXGE_REG_RD64(handle, offset,
258 NXGE_REG_RD64(handle, offset,
295 NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
349 NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
422 NXGE_REG_RD64(handl
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H A Dnpi_txc.c164 NXGE_REG_RD64(handle, offset, &value);
198 NXGE_REG_RD64(handle, txc_fzc_offset[i], &value);
236 NXGE_REG_RD64(handle, offset, &value);
397 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &txc_control_p->value);
436 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
463 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
529 NXGE_REG_RD64(handle, (TXC_TRAINING_REG & TXC_TRAINING_VECTOR_MASK),
557 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
584 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
729 NXGE_REG_RD64(handl
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H A Dnpi_txc.h68 NXGE_REG_RD64(handle, \
76 NXGE_REG_RD64(handle, \
H A Dnpi_espc.h42 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG),\
H A Dnpi_rxdma.c196 NXGE_REG_RD64(handle, rx_fzc_offset[i], &value);
239 NXGE_REG_RD64(handle, valid_offset, &page_vld.value);
282 NXGE_REG_RD64(handle, valid_offset, &page_vld.value);
872 NXGE_REG_RD64(handle, offset, &cnt->value);
917 NXGE_REG_RD64(handle, offset, &cnt.value);
1044 NXGE_REG_RD64(handle, pre_offset, &pre_log->value);
1045 NXGE_REG_RD64(handle, sha_offset, &sha_log->value);
1112 NXGE_REG_RD64(handle, pre_offset, &clr.value);
1135 NXGE_REG_RD64(handle, sha_offset, &clr.value);
1214 NXGE_REG_RD64(handl
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H A Dnpi_zcp.c51 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val);
79 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val);
131 NXGE_REG_RD64(handle, ZCP_INT_MASK_REG, &val);
168 NXGE_REG_RD64(handle, ZCP_INT_STAT_REG, &val);
198 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val);
635 NXGE_REG_RD64(handle, offset, &cfifo_reg.value);
715 NXGE_REG_RD64(handle, ZCP_RAM_DATA0_REG, &val->w0);
716 NXGE_REG_RD64(handle, ZCP_RAM_DATA1_REG, &val->w1);
717 NXGE_REG_RD64(handle, ZCP_RAM_DATA2_REG, &val->w2);
718 NXGE_REG_RD64(handl
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H A Dnpi_mac.h283 NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p))
289 NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p))
295 NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p))
301 NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p))
307 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
326 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
333 NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p))
H A Dnpi_ipp.c125 NXGE_REG_RD64(handle, (uint32_t)offset, &value);
127 NXGE_REG_RD64(handle, offset, &value);
155 NXGE_REG_RD64(handle, (uint32_t)offset, &value);
157 NXGE_REG_RD64(handle, offset, &value);
H A Dnpi_ipp.h124 NXGE_REG_RD64(handle, IPP_REG_ADDR(portn, reg), val);\
H A Dnpi_zcp.h117 NXGE_REG_RD64(handle, ZCP_RAM_ACC_REG, &val);\
H A Dnpi_txdma.h135 NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p)
H A Dnpi_txdma.c192 NXGE_REG_RD64(handle, (uint32_t)tx_fzc_offset[i], &value);
194 NXGE_REG_RD64(handle, tx_fzc_offset[i], &value);
1855 NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
1868 NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_common_impl.h314 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
324 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
329 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
H A Dnxge_fflp_hw.h1098 NXGE_REG_RD64((handle), (offset), (val_p))
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_txc.c570 NXGE_REG_RD64(nxgep->npi_handle, TXC_INT_STAT_DBG_REG,
H A Dnxge_zcp.c333 NXGE_REG_RD64(nxgep->npi_handle, ZCP_INT_STAT_TEST_REG,
H A Dnxge_intr.c1074 NXGE_REG_RD64(nxge->npi_handle, offset, value);
H A Dnxge_main.c1846 NXGE_REG_RD64(nxgep->npi_handle, reg, &regdata);

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