Searched +defs:val +defs:channel (Results 1 - 2 of 2) sorted by relevance

/solaris-x11-s12/open-src/kernel/i915/src/
H A Dintel_hdmi.c147 u32 val = I915_READ(VIDEO_DIP_CTL); local
150 if (!(val & VIDEO_DIP_ENABLE))
153 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
154 val |= g4x_infoframe_index(frame);
156 val &= ~g4x_infoframe_enable(frame);
158 I915_WRITE(VIDEO_DIP_CTL, val);
170 val |= g4x_infoframe_enable(frame);
171 val &= ~VIDEO_DIP_FREQ_MASK;
172 val |= VIDEO_DIP_FREQ_VSYNC;
174 I915_WRITE(VIDEO_DIP_CTL, val);
188 u32 val = I915_READ(reg); local
228 u32 val = I915_READ(reg); local
271 u32 val = I915_READ(reg); local
312 u32 val = I915_READ(ctl_reg); local
392 u32 val = I915_READ(reg); local
457 u32 val = I915_READ(reg); local
517 u32 val = I915_READ(reg); local
552 u32 val = I915_READ(reg); local
586 u32 val = I915_READ(reg); local
739 int channel = vlv_dport_to_channel(dport); local
960 intel_hdmi_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val) argument
1039 u32 val; local
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H A Dintel_dp.c88 DRM_ERROR("invalid max DP link bw val %x, using 1.62Gbps\n",
254 DRM_ERROR("eDP powered off while attempting aux channel communication.");
338 /* Try to wait for any previous AUX channel activity */
355 /* Load the send data into the aux channel data registers */
434 /* Write data to the aux channel in native mode */
467 /* Write a single byte to the aux channel in native mode */
475 /* read bytes from a native aux channel */
1012 * If the panel wasn't on, delay before accessing aux channel
1434 int channel = vlv_dport_to_channel(dport); local
1436 vlv_wait_port_ready(dev_priv, channel);
1455 u32 val; local
2016 uint32_t val; local
2024 I915_WRITE(DP_TP_CTL(port), val); local
2634 intel_dp_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t val) argument
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