Searched +defs:val +defs:channel (Results 1 - 24 of 24) sorted by relevance

/illumos-gate/usr/src/uts/common/os/
H A Dmove.c242 ureadc(int val, struct uio *uiop) argument
274 c = (unsigned char) (val & 0xFF);
449 dcopy_handle_t channel; local
465 channel = uioa->uioa_hwst[UIO_DCOPY_CHANNEL];
504 ret = dcopy_cmd_alloc(channel, dcopy_flags, &cmd);
588 dcopy_handle_t channel; local
596 error = dcopy_alloc(DCOPY_NOSLEEP, &channel);
607 uioap->uioa_hwst[UIO_DCOPY_CHANNEL] = channel;
714 dcopy_handle_t channel; local
725 channel
[all...]
/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txc.c256 * channel - channel number (0 - 23)
267 npi_txc_dma_max_burst(npi_handle_t handle, io_op_t op_mode, uint8_t channel, argument
270 uint64_t val; local
272 ASSERT(TXDMA_CHANNEL_VALID(channel));
273 if (!TXDMA_CHANNEL_VALID(channel)) {
276 " Invalid Input: channel <0x%x>",
277 channel));
278 return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(channel));
283 TXC_FZC_REG_READ64(handle, TXC_DMA_MAX_BURST_REG, channel,
319 npi_txc_dma_max_burst_set(npi_handle_t handle, uint8_t channel, uint32_t max_burst) argument
354 npi_txc_dma_bytes_transmitted(npi_handle_t handle, uint8_t channel, uint32_t *dma_bytes_p) argument
357 uint64_t val; local
431 uint64_t val; local
457 uint64_t val; local
527 uint64_t val; local
553 uint64_t val; local
580 uint64_t val; local
622 uint64_t val; local
648 npi_txc_port_dma_channel_enable(npi_handle_t handle, uint8_t port, uint8_t channel) argument
651 uint64_t val; local
686 npi_txc_port_dma_channel_disable(npi_handle_t handle, uint8_t port, uint8_t channel) argument
689 uint64_t val; local
725 uint64_t val; local
755 uint64_t val; local
1039 uint64_t val; local
[all...]
H A Dnpi_txdma.c36 uint8_t channel);
38 uint8_t channel);
40 uint8_t channel);
285 * channel - hardware TXDMA channel from 0 to 23.
297 npi_txdma_log_page_set(npi_handle_t handle, uint8_t channel, argument
302 uint64_t val; local
305 DMA_LOG_PAGE_FN_VALIDATE(channel, cfgp->page_num, cfgp->func_num,
314 TX_LOG_REG_WRITE64(handle, TX_LOG_PAGE_VLD_REG, channel, 0);
315 TX_LOG_REG_READ64(handle, TX_LOG_PAGE_VLD_REG, channel,
390 npi_txdma_log_page_get(npi_handle_t handle, uint8_t channel, p_dma_log_page_t cfgp) argument
395 uint64_t val; local
460 npi_txdma_log_page_handle_set(npi_handle_t handle, uint8_t channel, p_log_page_hdl_t hdl_p) argument
508 npi_txdma_log_page_config(npi_handle_t handle, io_op_t op_mode, txdma_log_cfg_t type, uint8_t channel, p_dma_log_page_t cfgp) argument
513 uint64_t val; local
668 npi_txdma_log_page_vld_config(npi_handle_t handle, io_op_t op_mode, uint8_t channel, p_log_page_vld_t vld_p) argument
739 npi_txdma_channel_reset(npi_handle_t handle, uint8_t channel) argument
766 npi_txdma_channel_init_enable(npi_handle_t handle, uint8_t channel) argument
790 npi_txdma_channel_enable(npi_handle_t handle, uint8_t channel) argument
814 npi_txdma_channel_disable(npi_handle_t handle, uint8_t channel) argument
838 npi_txdma_channel_resume(npi_handle_t handle, uint8_t channel) argument
861 npi_txdma_channel_mmk_clear(npi_handle_t handle, uint8_t channel) argument
885 npi_txdma_channel_mbox_enable(npi_handle_t handle, uint8_t channel) argument
919 npi_txdma_channel_control(npi_handle_t handle, txdma_cs_cntl_t control, uint8_t channel) argument
1036 npi_txdma_control_status(npi_handle_t handle, io_op_t op_mode, uint8_t channel, p_tx_cs_t cs_p) argument
1101 npi_txdma_event_mask(npi_handle_t handle, io_op_t op_mode, uint8_t channel, p_tx_dma_ent_msk_t mask_p) argument
1167 npi_txdma_event_mask_config(npi_handle_t handle, io_op_t op_mode, uint8_t channel, txdma_ent_msk_cfg_t *mask_cfgp) argument
1232 npi_txdma_event_mask_mk_out(npi_handle_t handle, uint8_t channel) argument
1269 npi_txdma_event_mask_mk_in(npi_handle_t handle, uint8_t channel) argument
1314 npi_txdma_ring_addr_set(npi_handle_t handle, uint8_t channel, uint64_t start_addr, uint32_t len) argument
1360 npi_txdma_ring_config(npi_handle_t handle, io_op_t op_mode, uint8_t channel, uint64_t *reg_data) argument
1418 npi_txdma_mbox_config(npi_handle_t handle, io_op_t op_mode, uint8_t channel, uint64_t *mbox_addr) argument
1657 npi_txdma_desc_kick_reg_set(npi_handle_t handle, uint8_t channel, uint16_t tail_index, boolean_t wrap) argument
1710 npi_txdma_desc_kick_reg_get(npi_handle_t handle, uint8_t channel, p_tx_ring_kick_t kick_p) argument
1750 npi_txdma_ring_head_get(npi_handle_t handle, uint8_t channel, p_tx_ring_hdl_t hdl_p) argument
1771 npi_txdma_channel_mbox_get(npi_handle_t handle, uint8_t channel, p_txdma_mailbox_t mbox_p) argument
1781 npi_txdma_channel_pre_state_get(npi_handle_t handle, uint8_t channel, p_tx_dma_pre_st_t prep) argument
1801 npi_txdma_ring_error_get(npi_handle_t handle, uint8_t channel, p_txdma_ring_errlog_t ring_errlog_p) argument
1979 npi_txdma_inj_int_error_set(npi_handle_t handle, uint8_t channel, p_tdmc_intr_dbg_t erp) argument
2002 npi_txdma_control_reset_wait(npi_handle_t handle, uint8_t channel) argument
2027 npi_txdma_control_stop_wait(npi_handle_t handle, uint8_t channel) argument
2052 npi_txdma_control_resume_wait(npi_handle_t handle, uint8_t channel) argument
[all...]
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_hw.c327 uint16_t val; local
343 BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) {
373 if (val == 0x639C) {
459 * channel specific errors are reported on a per channel basis.
537 uint8_t channel; local
557 channel = ldvp->channel;
559 channel, count);
561 channel, tick
876 nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp, uint32_t reg_base, uint16_t channel, uint64_t reg_data) argument
897 nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp, uint32_t reg_base, uint16_t channel) argument
[all...]
H A Dnxge_kstats.c526 int channel; local
537 channel = mi_strtol(ch_name, &end, 10);
540 statsp = (p_nxge_tx_ring_stats_t)&nxgep->statsp->tdc_stats[channel];
543 "nxge_tdc_stat_update data $%p statsp $%p channel %d",
544 ksp->ks_data, statsp, channel));
595 int channel; local
606 channel = mi_strtol(ch_name, &end, 10);
609 statsp = (p_nxge_rx_ring_stats_t)&nxgep->statsp->rdc_stats[channel];
612 "nxge_rdc_stat_update $%p statsp $%p channel %d",
613 ksp->ks_data, statsp, channel));
1187 nxge_setup_rdc_kstats(p_nxge_t nxgep, int channel) argument
1208 nxge_setup_tdc_kstats(p_nxge_t nxgep, int channel) argument
1910 uint64_t val; local
2112 uint64_t val = 0; local
2158 uint64_t val = 0; local
2197 nxge_rx_ring_stat(mac_ring_driver_t rdriver, uint_t stat, uint64_t *val) argument
2237 nxge_tx_ring_stat(mac_ring_driver_t rdriver, uint_t stat, uint64_t *val) argument
2279 uint64_t val = 0; local
[all...]
H A Dnxge_main.c834 /* Find our VR & channel sets. */
1635 * enable the port, configure the dma channel bitmap,
2289 * Assume that each DMA channel will be configured with
2436 * channel The channel to map into our kernel space.
2456 int channel)
2479 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
2480 num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel];
2483 nxgep, channel, data, rx_buf_alloc_size,
2489 "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *dat
2454 nxge_alloc_rxb( p_nxge_t nxgep, int channel) argument
2512 nxge_free_rxb( p_nxge_t nxgep, int channel) argument
2906 nxge_alloc_txb( p_nxge_t nxgep, int channel) argument
2966 nxge_free_txb( p_nxge_t nxgep, int channel) argument
4713 uint64_t val = statsp->mac_stats.link_speed * 1000000ull; local
5541 uint32_t channel; local
5560 uint32_t channel; local
5577 uint32_t channel; local
5615 uint32_t channel; local
5631 nxge_ring_get_htable_idx(p_nxge_t nxgep, mac_ring_type_t type, uint32_t channel) argument
5679 uint32_t channel; local
5792 uint16_t channel; /* device-wise ring id */ local
5862 uint16_t channel; /* device-wise ring id */ local
[all...]
/illumos-gate/usr/src/lib/libdladm/common/
H A Dlibdlwlan.c442 dladm_wlan_channel_t channel; local
448 channel = attrp->wa_channel;
449 status = do_set_channel(handle, linkid, &channel);
499 status = do_set_channel(handle, linkid, &channel);
891 find_name_by_val(uint_t val, val_desc_t *vdp, uint_t cnt, char **strp) argument
896 if (val == vdp[i].vd_val) {
919 dladm_wlan_val2str(uint_t val, val_desc_t *vdp, uint_t cnt, char *buf) argument
923 if (!find_name_by_val(val, vdp, cnt, &s))
1013 uint_t val; local
1015 if (!find_val_by_name(str, secmode_vals, VALCNT(secmode_vals), &val))
1025 uint_t val; local
1037 uint_t val; local
1056 uint_t val; local
1068 uint_t val; local
1080 uint_t val; local
1378 do_set_channel(dladm_handle_t handle, datalink_id_t linkid, dladm_wlan_channel_t *channel) argument
1610 add_new_property(scf_handle_t *handle, const char *prop_name, scf_type_t type, const char *val, scf_transaction_t *tx) argument
[all...]
H A Dlinkprop.c484 { "channel", { NULL, 0 },
3143 char val[DLADM_PROP_VAL_MAX]; local
3158 bcopy(*prop_val, val, DLADM_PROP_VAL_MAX);
3159 module = strtok(val, delimiters);
3371 uint32_t channel; local
3381 if (!i_dladm_wlan_convert_chan(&wl_phy_conf, &channel))
3384 (void) snprintf(*prop_val, DLADM_STRSIZE, "%u", channel);
3755 void *val; local
3762 val = (void *)vdp->vd_val;
3771 val
4286 int val, i; local
4414 uint_t val; local
[all...]
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhxge_kstats.c355 int channel; local
365 channel = mi_strtol(ch_name, &end, 10);
368 statsp = (p_hxge_tx_ring_stats_t)&hxgep->statsp->tdc_stats[channel];
371 "hxge_tdc_stat_update data $%p statsp $%p channel %d",
372 ksp->ks_data, statsp, channel));
443 int channel; local
454 channel = mi_strtol(ch_name, &end, 10);
457 statsp = (p_hxge_rx_ring_stats_t)&hxgep->statsp->rdc_stats[channel];
460 "hxge_rdc_stat_update $%p statsp $%p channel %d",
461 ksp->ks_data, statsp, channel));
776 int channel; local
888 hxge_rx_ring_stat(mac_ring_driver_t rdriver, uint_t stat, uint64_t *val) argument
920 hxge_tx_ring_stat(mac_ring_driver_t rdriver, uint_t stat, uint64_t *val) argument
954 uint64_t val = 0; local
955 int channel; local
[all...]
/illumos-gate/usr/src/uts/sun4u/tazmo/io/
H A Denvctrl.c1500 fan.val = INIT_FAN_VAL;
1548 if (fanspeed->val > MAX_FAN_VAL) {
1554 buf[0] = fanspeed->val;
1582 fanspeed->val;
1586 fanspeed->val;
1590 fanspeed->val;
1598 buf[0] = ioport->val;
1728 ioport->val = buf[0];
1953 fspchip.val = (fspchip.val
2453 envctrl_add_encl_kstats(struct envctrlunit *unitp, int type, int instance, uint8_t val) argument
2893 envctrl_set_fsp(struct envctrlunit *unitp, uint8_t *val) argument
3188 uint8_t val; local
3253 envctrl_mod_encl_kstats(struct envctrlunit *unitp, int type, int instance, uint8_t val) argument
3990 eHc_read_pcf8591(struct eHc_envcunit *ehcp, int byteaddress, int channel, int autoinc, int amode, int aenable, uint8_t *buf, int size) argument
[all...]
/illumos-gate/usr/src/uts/intel/io/intel_nb5000/
H A Dnb5000_init.c180 int channel = bus & 1; local
182 rt = SPD_RD(branch, channel);
188 write_spdcmd(int bus, uint32_t val) argument
191 int channel = bus & 1; local
192 SPDCMD_WR(branch, channel, val);
285 fbd_eeprom(int channel, int dimm, nb_dimm_t *dp) argument
290 t = read_spd_eeprom(channel, dimm, 0) & 0xf;
297 dp->manufacture_id = read_spd_eeprom(channel, dimm, 117) |
298 (read_spd_eeprom(channel, dim
322 ddr2_eeprom(int channel, int dimm, nb_dimm_t *dp) argument
380 nb_dimm_present(int channel, int dimm) argument
399 nb_ddr2_dimm_init(int channel, int dimm, int start_rank) argument
419 nb_fbd_dimm_init(int channel, int dimm, uint16_t mtr) argument
733 int channel = dimm >> 3; local
752 int channel = dimm / nb_dimms_per_channel; local
766 nb_rank2dimm(int channel, int rank) argument
[all...]
/illumos-gate/usr/src/uts/intel/io/dktp/controller/ata/
H A Data_common.c1519 ushort_t val; local
1525 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS);
1526 if ((val & onbits) == onbits && (val & offbits) == 0)
1553 ushort_t val; local
1558 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS);
1563 if ((val & onbits1) == onbits1 && (val & offbits1) == 0)
1569 if ((val & failure_onbits2) == failure_onbits2 &&
1570 (val
2139 int simplex_dma_channel, *rp, proplen, channel; local
[all...]
/illumos-gate/usr/src/uts/common/io/arn/
H A Darn_main.c250 arn_iowrite32(struct ath_hal *ah, uint32_t reg_offset, uint32_t val) argument
256 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)), val);
260 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)), val);
267 uint32_t val; local
271 val = ddi_get32(sc->sc_io_handle,
275 val = ddi_get32(sc->sc_io_handle,
279 return (val);
691 "unable to collect channel list; "
698 "number of channel is %d\n", nchan));
703 index = ath9k_hw_mhz2ieee(ah, c->channel,
1398 struct ath9k_channel *channel; local
2197 arn_m_stat(void *arg, uint_t stat, uint64_t *val) argument
2337 uint32_t val, index, bit; local
2798 uint32_t val; local
[all...]
/illumos-gate/usr/src/uts/common/io/
H A Dbscbus.c249 ddi_acc_handle_t ch_handle; /* per channel access handle */
251 unsigned int map_count; /* Number of mappings to channel */
252 boolean_t map_dog; /* channel is mapped for watchdog */
316 * Flag to indicate that we are using per channel
327 * channel state data, protected by ch_mutex
328 * channel claim/release requests are protected by this mutex.
331 struct bscbus_channel_state channel[BSCBUS_MAX_CHANNELS]; member in struct:bscbus_state
458 bscbus_put_reg(struct bscbus_channel_state *csp, uint_t reg, uint8_t val) argument
462 csp->ch_regs + reg, val);
469 uint8_t val; local
499 bscbus_pat_dog(struct bscbus_channel_state *csp, uint8_t val) argument
926 bscbus_cmd(HANDLE_TYPE *hdlp, ptrdiff_t vreg, uint_t val, uint_t cmd) argument
1094 bscbus_vreg_put8(HANDLE_TYPE *hdlp, uint8_t *addr, uint8_t val) argument
1177 bscbus_pat_put8(HANDLE_TYPE *hdlp, uint8_t *addr, uint8_t val) argument
1256 bscbus_event_put16(HANDLE_TYPE *hdlp, uint16_t *addr, uint16_t val) argument
1362 bscbus_meta_put32(HANDLE_TYPE *hdlp, uint32_t *addr, uint32_t val) argument
1442 bscbus_no_put8(HANDLE_TYPE *hdlp, uint8_t *addr, uint8_t val) argument
1489 bscbus_no_put16(HANDLE_TYPE *hdlp, uint16_t *addr, uint16_t val) argument
1536 bscbus_no_put64(HANDLE_TYPE *hdlp, uint64_t *addr, uint64_t val) argument
[all...]
/illumos-gate/usr/src/uts/common/io/usb/clients/audio/usb_ac/
H A Dusb_ac.c760 int val; local
789 val = (int)val1;
793 "val=0x%x(%d)", val1, val1, val, val);
804 uacp, val);
1039 uint_t channel, uint_t control)
1044 channel, control, USB_AC_FIND_ONE, &count, 0,
1051 * check if a feature unit can support the required channel
1058 uint_t dir, uint_t channel, uint_
1038 usb_ac_get_featureID(usb_ac_state_t *uacp, uchar_t dir, uint_t channel, uint_t control) argument
1057 usb_ac_feature_unit_check(usb_ac_state_t *uacp, uint_t featureID, uint_t dir, uint_t channel, uint_t control, uint_t arg1, uint_t *depth) argument
1798 usb_ac_update_port(usb_ac_state_t *uacp, uint_t id, uint_t dir, uint_t channel, uint_t control, uint_t arg1, uint_t *depth) argument
1892 usb_ac_match_port(usb_ac_state_t *uacp, uint_t id, uint_t dir, uint_t channel, uint_t control, uint_t arg1, uint_t *depth) argument
1931 usb_ac_set_selector(usb_ac_state_t *uacp, uint_t id, uint_t dir, uint_t channel, uint_t control, uint_t arg1, uint_t *depth) argument
2051 usb_ac_set_control(usb_ac_state_t *uacp, uint_t dir, uint_t search_target, uint_t channel, uint_t control, uint_t all_or_one, uint_t *count, uint_t arg1, int (*func)(usb_ac_state_t *uacp, uint_t unit, uint_t dir, uint_t channel, uint_t control, uint_t arg1, uint_t *depth)) argument
2087 usb_ac_traverse_all_units(usb_ac_state_t *uacp, uint_t dir, uint_t search_target, uint_t channel, uint_t control, uint_t all_or_one, uint_t *count, uint_t arg1, uint_t *depth, int (*func)(usb_ac_state_t *uacp, uint_t unit, uint_t dir, uint_t channel, uint_t control, uint_t arg1, uint_t *depth)) argument
2159 usb_ac_set_monitor_gain_control(usb_ac_state_t *uacp, uint_t dir, uint_t search_target, uint_t channel, uint_t control, uint_t all_or_one, uint_t *count, uint_t arg1, int (*func)(usb_ac_state_t *uacp, uint_t unit, uint_t dir, uint_t channel, uint_t control, uint_t arg1, uint_t *depth)) argument
2269 usb_ac_traverse_connections(usb_ac_state_t *uacp, uint_t start_unit, uint_t dir, uint_t search_target, uint_t channel, uint_t control, uint_t all_or_one, uint_t *count, uint_t arg1, uint_t *depth, int (*func)(usb_ac_state_t *uacp, uint_t unit, uint_t dir, uint_t channel, uint_t control, uint_t arg1, uint_t *depth)) argument
2794 usb_ac_set_monitor_gain(usb_ac_state_t *uacp, uint_t unit, uint_t dir, uint_t channel, uint_t control, uint_t gain, uint_t *depth) argument
2878 usb_ac_set_gain(usb_ac_state_t *uacp, uint_t featureID, uint_t dir, uint_t channel, uint_t control, uint_t gain, uint_t *depth) argument
3246 usb_ac_get_maxmin_volume(usb_ac_state_t *uacp, uint_t channel, int cmd, int dir, int feature_unitID, short *max_or_minp) argument
3302 usb_ac_set_volume(usb_ac_state_t *uacp, uint_t channel, short gain, int dir, int feature_unitID) argument
3358 usb_ac_set_mute(usb_ac_state_t *uacp, uint_t featureID, uint_t dir, uint_t channel, uint_t control, uint_t muteval, uint_t *depth) argument
4540 uint_t val, fmt_sr; local
5052 usb_audio_ctrl_alloc(usb_ac_state_t *statep, uint32_t num, uint64_t val) argument
5606 uint64_t val; local
[all...]
/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-device.c30 #include "xgehal-channel.h"
87 __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, void *addr) argument
90 xge_os_pio_mem_write32(pdev, regh, val, addr);
92 xge_os_pio_mem_write32(pdev, regh, val, (void *)((char *)addr + 4));
104 __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val, argument
108 xge_os_pio_mem_write32(pdev, regh, val,
111 xge_os_pio_mem_write32(pdev, regh, val, addr);
2188 u8 val; local
2227 xge_offsetof(xge_hal_pci_config_le_t, latency_timer), &val);
2228 hldev->config.latency_timer = val;
3050 u32 val = (u32)(XGE_HAL_SW_RESET_ALL >> 32); local
3214 xge_hal_channel_t channel; local
4445 __hal_device_msix_intr_endis(xge_hal_device_t *hldev, xge_hal_channel_t *channel, int flag) argument
4481 xge_hal_channel_h channel; local
4536 xge_hal_channel_t *channel; local
4549 xge_hal_channel_t *channel; local
4595 xge_hal_channel_t *channel; local
4613 xge_hal_channel_t *channel; local
4653 xge_hal_channel_h channel; local
5142 xge_hal_channel_t *channel; local
5435 xge_hal_channel_t *channel; local
5504 xge_hal_channel_t *channel = (xge_hal_channel_t*) local
5642 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
6451 __hal_device_rti_set(int ring_qid, xge_hal_channel_t *channel) argument
6477 __hal_device_tti_set(int fifo_qid, xge_hal_channel_t *channel) argument
6509 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
6656 xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh; local
[all...]
/illumos-gate/usr/src/uts/common/io/iwk/
H A Diwk2.c296 static int iwk_txpower_grp(uint16_t channel);
298 uint16_t channel,
300 static int32_t iwk_band_number(iwk_sc_t *sc, uint16_t channel);
304 static int iwk_channel_interpolate(iwk_sc_t *sc, uint16_t channel,
332 static int iwk_m_stat(void *arg, uint_t stat, uint64_t *val);
1614 /* step to next channel before actual FW scan */
1644 * channel same to the target AP...
2135 len, stat->rate.r.s.rate, LE_16(stat->channel),
2319 /* enable each channel 0-7 */
2428 "scanning channel
3148 iwk_m_stat(void *arg, uint_t stat, uint64_t *val) argument
4491 iwk_txpower_grp(uint16_t channel) argument
4555 iwk_get_eep_channel(iwk_sc_t *sc, uint16_t channel, int is_24G, int is_fat, int is_hi_chan) argument
4616 iwk_band_number(iwk_sc_t *sc, uint16_t channel) argument
4662 int32_t val; local
4673 iwk_channel_interpolate(iwk_sc_t *sc, uint16_t channel, struct iwk_eep_calib_channel_info *chan_info) argument
4816 uint16_t channel; local
[all...]
H A Diwk_hw.h253 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
356 * Rx Config Reg for channel 0 (only channel used)
366 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
403 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
404 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
424 * To use a Tx DMA channel, driver must initialize its
433 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
453 * After stopping Tx DMA channel (writing 0 to
455 * IWK_FH_TSSR_TX_STATUS_REG until selected Tx channel i
2238 uint16_t channel; member in struct:iwk_tx_power_table_cmd
2245 uint16_t channel; member in struct:iwk_channel_switch_cmd
2254 uint16_t channel; member in struct:iwk_channel_switch_notif
2399 uint16_t channel; /* channel number */ member in struct:iwk_rx_phy_res
2433 uint16_t val; member in struct:iwk_queue_byte_cnt_entry
[all...]
/illumos-gate/usr/src/uts/sun4u/opl/io/
H A Ddrmach.c181 int channel; member in struct:drmach_io
858 drmach_array_set(drmach_array_t *arr, int idx, drmachid_t val) argument
863 arr->arr[idx - arr->min_index] = val;
870 drmach_array_get(drmach_array_t *arr, int idx, drmachid_t *val) argument
875 *val = arr->arr[idx - arr->min_index];
882 drmach_array_first(drmach_array_t *arr, int *idx, drmachid_t *val) argument
887 while ((rv = drmach_array_get(arr, *idx, val)) == 0 && *val == NULL)
894 drmach_array_next(drmach_array_t *arr, int *idx, drmachid_t *val) argument
899 while ((rv = drmach_array_get(arr, *idx, val))
908 drmachid_t val; local
[all...]
/illumos-gate/usr/src/uts/sun4u/starfire/io/
H A Didn_proto.c104 static int idn_send_mboxdata(int domid, struct idn *sip, int channel,
106 static int idn_recv_mboxdata(int channel, caddr_t bufp);
120 idn_mainmbox_t *recv_mmp, int channel);
121 static int idn_mainmbox_chan_unregister(ushort_t domset, int channel);
128 static int idn_deactivate_channel_services(int channel,
130 static int idn_activate_channel_services(int channel);
135 static void idn_chan_action(int channel, idn_chanaction_t chanaction,
137 static void idn_chan_addmbox(int channel, ushort_t domset);
138 static void idn_chan_delmbox(int channel, ushort_t domset);
139 static void idn_submit_chanactivate_job(int channel);
4842 int channel; local
6465 uint_t val; local
10132 idn_mainmbox_chan_register(int domid, idn_mainmbox_t *send_mmp, idn_mainmbox_t *recv_mmp, int channel) argument
10185 idn_mainmbox_chan_unregister(ushort_t domset, int channel) argument
10231 idn_domain_is_registered(int domid, int channel, idn_chanset_t *chansetp) argument
10488 idn_chan_server_syncheader(int channel) argument
10609 int channel; local
11093 idn_chan_action(int channel, idn_chanaction_t chanaction, int wait) argument
11317 idn_chan_addmbox(int channel, ushort_t domset) argument
11367 idn_chan_delmbox(int channel, ushort_t domset) argument
11467 idn_send_mboxdata(int domid, struct idn *sip, int channel, caddr_t bufp) argument
11623 idn_recv_mboxdata(int channel, caddr_t bufp) argument
11727 idn_reclaim_mboxdata(int domid, int channel, int nbufs) argument
11950 idn_signal_data_server(int domid, ushort_t channel) argument
12196 idn_open_channel(int channel) argument
12275 idn_close_channel(int channel, idn_chanop_t chanop) argument
12522 idn_activate_channel_services(int channel) argument
12596 idn_deactivate_channel_services(int channel, idn_chanop_t chanop) argument
12766 int not_active, channel; local
12809 idn_submit_chanactivate_job(int channel) argument
[all...]
/illumos-gate/usr/src/uts/sun4v/io/
H A Dvds.c79 #define VD_CHANNEL_ENDPOINT "channel-endpoint"
261 #define VDS_SET_MDEG_PROP_INST(specp, val) (specp)[1].ps_val = (val);
500 boolean_t reset_ldc; /* reset LDC channel? */
587 * fails to reset disk exclusive access when a LDC channel is reset. When a
588 * LDC channel is reset the vdisk server will try to reset disk exclusive
2312 PR0("taking down LDC channel");
4368 * communication on this channel now
5242 * check if channel is UP - else break out of loop
5246 PR0("channel no
5368 vds_check_for_vd(mod_hash_key_t key, mod_hash_val_t *val, void *arg) argument
7015 vds_do_get_ldc_id(md_t *md, mde_cookie_t vd_node, mde_cookie_t *channel, uint64_t *ldc_id) argument
7048 mde_cookie_t *channel; local
[all...]
/illumos-gate/usr/src/uts/common/io/cxgbe/common/
H A Dt4_msg.h293 __u8 channel:2; member in struct:rss_header
305 __u8 channel:2; member in struct:rss_header
747 __be64 val; member in struct:cpl_set_tcb_field
1990 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
/illumos-gate/usr/src/uts/common/io/iwh/
H A Diwh_hw.h255 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
357 * Rx Config Reg for channel 0 (only channel used)
367 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
404 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
405 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
425 * To use a Tx DMA channel, driver must initialize its
431 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
444 * After stopping Tx DMA channel (writing 0 to
445 * IWH_FH_TSSR_TX_STATUS_REG until selected Tx channel i
1489 uint8_t channel; member in struct:iwh_tx_power_table_cmd
1630 uint16_t channel; /* channel number */ member in struct:iwh_rx_phy_res
1675 uint16_t val; member in struct:iwh_queue_byte_cnt_entry
[all...]
/illumos-gate/usr/src/uts/common/io/iwp/
H A Diwp_hw.h252 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
354 * Rx Config Reg for channel 0 (only channel used)
364 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
401 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
402 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
422 * To use a Tx DMA channel, driver must initialize its
428 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
441 * After stopping Tx DMA channel (writing 0 to
442 * IWP_FH_TSSR_TX_STATUS_REG until selected Tx channel i
1489 uint8_t channel; member in struct:iwp_tx_power_table_cmd
1630 uint16_t channel; /* channel number */ member in struct:iwp_rx_phy_res
1675 uint16_t val; member in struct:iwp_queue_byte_cnt_entry
[all...]

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