Searched refs:Write (Results 1 - 25 of 190) sorted by relevance

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/vbox/src/libs/xpcom18a4/java/tools/genifaces/
H A DGenerateJavaInterfaces.cpp387 nsresult rv = out->Write(kHeader1, sizeof(kHeader1) - 1, &count);
394 rv = out->Write(searchTerm.get(), PR_MIN(29, searchTerm.Length()), &count);
397 rv = out->Write(kHeader2, sizeof(kHeader2) - 1, &count);
399 rv = out->Write(kPackage, sizeof(kPackage) - 1, &count);
413 nsresult rv = out->Write(kIfaceDecl1, sizeof(kIfaceDecl1) - 1, &count);
415 rv = out->Write(iface_name, strlen(iface_name), &count);
421 rv = out->Write(kParentDecl, sizeof(kParentDecl) - 1, &count);
423 rv = out->Write(parent_name, strlen(parent_name), &count);
427 rv = out->Write(kIfaceDecl2, sizeof(kIfaceDecl2) - 1, &count);
434 return out->Write("}\
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/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkPkg/Include/Protocol/
H A DBootScriptSave.h80 EFI_BOOT_SCRIPT_WRITE Write; ///< Writes various boot scripts to a boot script table. member in struct:_EFI_BOOT_SCRIPT_SAVE_PROTOCOL
H A DSmmCpuIo.h69 EFI_SMM_CPU_IO Write; member in struct:__anon10771
H A DFrameworkFirmwareVolumeBlock.h200 The Write() function writes the specified number of bytes from
204 EFI_FVB_ERASE_POLARITY state before calling the Write()
209 calling the Write() function, the caller should call the
215 state. If it is in this state, the Write() function must
217 contents of the firmware volume. The Write() function must
224 fully flushed to the hardware before the Write() service
343 FRAMEWORK_EFI_FVB_WRITE Write; member in struct:_FRAMEWORK_EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL
/vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/PciBusDxe/
H A DPciPowerManagement.c76 // Write PMCSR
78 Status = PciIoDevice->PciIo.Pci.Write (
H A DPciResourceSupport.c1304 PciIo->Pci.Write (
1321 PciIo->Pci.Write (
1331 PciIo->Pci.Write (
1386 PciIo->Pci.Write (
1402 PciIo->Pci.Write (
1412 PciIo->Pci.Write (
1475 PciIo->Pci.Write (
1491 PciIo->Pci.Write (
1500 PciIo->Pci.Write (
1510 PciIo->Pci.Write (
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H A DPciEnumeratorSupport.c512 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);
514 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
537 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
539 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
750 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT32)Offset, 1, &gAllOne);
754 // Write back the original value
756 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT32)Offset, 1, &OriginalValue);
815 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);
819 // Write back the original value
821 PciIo->Pci.Write (PciI
[all...]
/vbox/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Protocol/
H A DSmmCpuIo2.h77 EFI_SMM_CPU_IO2 Write; member in struct:__anon12301
H A DCpuIo2.h62 The Io.Read() and Io.Write() functions enable a driver to access PCI controller
122 EFI_CPU_IO_PROTOCOL_IO_MEM Write; member in struct:__anon12036
H A DDebugPort.h121 EFI_DEBUGPORT_WRITE Write; member in struct:_EFI_DEBUGPORT_PROTOCOL
H A DS3SaveState.h85 @param[in] OpCode The operation code (opcode) number. See "Related Definitions" in Write() for the
168 EFI_S3_SAVE_STATE_WRITE Write; member in struct:_EFI_S3_SAVE_STATE_PROTOCOL
H A DSuperIo.h43 @param[in] Write Specifies the type of the register operation. If this parameter is TRUE, Value is
54 @param[in, out] Value If Write is TRUE, Value is a pointer to the buffer containing the byte of data to be
55 written to the Super I/O register. If Write is FALSE, Value is a pointer to the
67 IN BOOLEAN Write,
/vbox/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/
H A DIdeController.c456 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 6, 1, (void *)&u8DH);
459 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 2, 1, (void *)&u8CS);
460 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 3, 1, (void *)&u8SN);
463 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 2, 1, (void *)&u8CS);
464 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 3, 1, (void *)&u8SN);
467 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 2, 1, (void *)&u8CS);
468 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 3, 1, (void *)&u8SN);
483 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 2, 1, (void *)&u8CS);
484 pPciIo->Io.Write(pPciIo, EfiPciIoWidthUint8, EFI_PCI_IO_PASS_THROUGH_BAR, u64IoBase + 3, 1, (void *)&u8SN);
/vbox/src/VBox/Devices/PC/ipxe/src/include/ipxe/efi/Protocol/
H A DCpuIo2.h64 The Io.Read() and Io.Write() functions enable a driver to access PCI controller
124 EFI_CPU_IO_PROTOCOL_IO_MEM Write; member in struct:__anon15604
/vbox/src/VBox/Devices/PC/ipxe/src/interface/efi/
H A Defi_io.c100 * Write to device
112 cpu_io->Io.Write : cpu_io->Mem.Write );
160 cpu_io->Io.Write : cpu_io->Mem.Write );
175 /* Write to non-existent port. Probably x86-only. */
/vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.c57 Write data to UHCI register.
73 Status = PciIo->Io.Write (
83 DEBUG ((EFI_D_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));
136 are Write-Clean.
244 Status = PciIo->Io.Write (
254 DEBUG ((EFI_D_ERROR, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status));
274 PciIo->Pci.Write (
/vbox/src/libs/xpcom18a4/xpcom/ds/
H A DnsHashtable.h87 virtual nsresult Write(nsIObjectOutputStream* aStream) const;
107 // Enumerator and Read/Write callback functions.
159 nsresult Write(nsIObjectOutputStream* aStream,
275 nsresult Write(nsIObjectOutputStream* aStream) const;
377 nsresult Write(nsIObjectOutputStream* aStream) const;
405 nsresult Write(nsIObjectOutputStream* aStream) const;
439 nsresult Write(nsIObjectOutputStream* aStream) const;
/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/
H A DLegacyIde.c290 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x10, 1, &IOBarClear);
291 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x14, 1, &IOBarClear);
294 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x18, 1, &IOBarClear);
295 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1C, 1, &IOBarClear);
/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkPkg/Include/Ppi/
H A DPciCfg.h98 /// PCI write services. See the Write() function description.
100 EFI_PEI_PCI_CFG_PPI_IO Write; member in struct:_EFI_PEI_PCI_CFG_PPI
/vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Include/Protocol/
H A DFaultTolerantWrite.h2 Fault Tolerant Write protocol provides boot-time service for fault tolerant
199 EFI_FAULT_TOLERANT_WRITE_WRITE Write; member in struct:_EFI_FAULT_TOLERANT_WRITE_PROTOCOL
/vbox/src/VBox/Devices/EFI/Firmware/MdeModulePkg/Universal/Network/SnpDxe/
H A DCallback.c195 mPciIo->Io.Write (
217 mPciIo->Mem.Write (
347 Snp->PciIo->Io.Write (
369 Snp->PciIo->Mem.Write (
/vbox/src/VBox/Devices/EFI/Firmware/MdePkg/Include/Ppi/
H A DPciCfg2.h173 EFI_PEI_PCI_CFG2_PPI_IO Write; member in struct:_EFI_PEI_PCI_CFG2_PPI
/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkModulePkg/Bus/Isa/Ps2MouseAbsolutePointerDxe/
H A DCommPs2.c566 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_CMD_STS_PORT, 1, &Data);
602 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_DATA_PORT, 1, &Temp);
686 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_CMD_STS_PORT, 1, &Data);
695 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_DATA_PORT, 1, &Command);
765 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_CMD_STS_PORT, 1, &Temp);
773 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_DATA_PORT, 1, &Temp);
/vbox/src/VBox/Devices/EFI/Firmware/IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/
H A DCommPs2.c565 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_CMD_STS_PORT, 1, &Data);
601 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_DATA_PORT, 1, &Temp);
685 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_CMD_STS_PORT, 1, &Data);
694 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_DATA_PORT, 1, &Command);
764 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_CMD_STS_PORT, 1, &Temp);
772 IsaIo->Io.Write (IsaIo, EfiIsaIoWidthUint8, KBC_DATA_PORT, 1, &Temp);
/vbox/src/VBox/Devices/EFI/Firmware/OptionRomPkg/CirrusLogic5430Dxe/
H A DCirrusLogic5430GraphicsOutput.c394 Private->PciIo->Mem.Write (
403 Private->PciIo->Mem.Write (
416 Private->PciIo->Mem.Write (
425 Private->PciIo->Mem.Write (
455 Private->PciIo->Mem.Write (
464 Private->PciIo->Mem.Write (

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