4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync The UHCI register operation routines.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncCopyright (c) 2007, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncThis program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncare licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncwhich accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncTHE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncWITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Read a UHCI register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PciIo The EFI_PCI_IO_PROTOCOL to use.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Offset Register offset to USB_BAR_INDEX.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @return Content of register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DEBUG ((EFI_D_ERROR, "UhciReadReg: PciIo Io.Read error: %r at offset %d\n", Status, Offset));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Write data to UHCI register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PciIo The EFI_PCI_IO_PROTOCOL to use.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Offset Register offset to USB_BAR_INDEX.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Data Data to write.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DEBUG ((EFI_D_ERROR, "UhciWriteReg: PciIo Io.Write error: %r at offset %d\n", Status, Offset));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Set a bit of the UHCI Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PciIo The EFI_PCI_IO_PROTOCOL to use.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Offset Register offset to USB_BAR_INDEX.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Bit The bit to set.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Clear a bit of the UHCI Register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PciIo The PCI_IO protocol to access the PCI.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Offset Register offset to USB_BAR_INDEX.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Bit The bit to clear.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Clear all the interrutp status bits, these bits
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are Write-Clean.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Uhc The UHCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // If current HC is halted, re-enable it. Host Controller Process Error
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // is a temporary error status.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DEBUG ((EFI_D_ERROR, "UhciAckAllInterrupt: re-enable the UHCI from system error\n"));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Uhc->Usb2Hc.SetState (&Uhc->Usb2Hc, EfiUsbHcStateOperational);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Stop the host controller.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Uhc The UHCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Timeout Max time allowed.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The host controller is stopped.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_TIMEOUT Failed to stop the host controller.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UhciClearRegBit (Uhc->PciIo, USBCMD_OFFSET, USBCMD_RS);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // ensure the HC is in halt status after send the stop command
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Timeout is in us unit.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync for (Index = 0; Index < (Timeout / 50) + 1; Index++) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Check whether the host controller operates well.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PciIo The PCI_IO protocol to use.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval TRUE Host controller is working.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval FALSE Host controller is halted or system error.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if ((UsbSts & (USBSTS_HCPE | USBSTS_HSE | USBSTS_HCH)) != 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DEBUG ((EFI_D_ERROR, "UhciIsHcWorking: current USB state is %x\n", UsbSts));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Set the UHCI frame list base address. It can't use
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UhciWriteReg which access memory in UINT16.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PciIo The EFI_PCI_IO_PROTOCOL to use.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param Addr Address to set.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DEBUG ((EFI_D_ERROR, "UhciSetFrameListBaseAddr: PciIo Io.Write error: %r\n", Status));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Disable USB Emulation.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.