Searched refs:TCG_AREG0 (Results 1 - 4 of 4) sorted by relevance

/vbox/src/recompiler/tcg/i386/
H A Dtcg-target.h123 # define TCG_AREG0 TCG_REG_R14 macro
126 # define TCG_AREG0 TCG_REG_EBP macro
128 # define TCG_AREG0 TCG_REG_ESI macro
H A Dtcg-target.c1115 tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, r1, TCG_AREG0, r1, 0,
/vbox/src/recompiler/
H A Dtranslate-all.c57 tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf),
/vbox/src/recompiler/target-i386/
H A Dtranslate.c8075 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8076 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
8078 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
8080 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
8082 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
8086 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
8088 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
8090 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
8092 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
8094 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
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