Searched refs:BASE (Results 1 - 18 of 18) sorted by relevance

/vbox/src/VBox/Additions/x11/x11include/mesa-7.2/src/mesa/sparc/
H A Dsparc_matrix.h52 #define LDMATRIX_0_1_2_3_12_13_14_15(BASE) \
53 ldd [BASE + ( 0 * 0x4)], M0; \
54 ldd [BASE + ( 2 * 0x4)], M2; \
55 ldd [BASE + (12 * 0x4)], M12; \
56 ldd [BASE + (14 * 0x4)], M14
58 #define LDMATRIX_0_1_12_13(BASE) \
59 ldd [BASE + ( 0 * 0x4)], M0; \
60 ldd [BASE + (12 * 0x4)], M12
62 #define LDMATRIX_0_12_13(BASE) \
63 ld [BASE
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/vbox/src/libs/zlib-1.2.6/
H A Dadler32.c14 #define BASE 65521 /* largest prime smaller than 65536 */ macro
16 /* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */
27 /* note that this assumes BASE is 65521, where 65536 % 65521 == 15
38 if (a >= BASE) a -= BASE; \
56 if (a >= BASE) a -= BASE; \
59 # define MOD(a) a %= BASE
60 # define MOD28(a) a %= BASE
61 # define MOD63(a) a %= BASE
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/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/
H A D3c595.c77 outw(RX_DISABLE, BASE + VX_COMMAND);
78 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
80 outw(TX_DISABLE, BASE + VX_COMMAND);
81 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
83 outw(RX_RESET, BASE + VX_COMMAND);
85 outw(TX_RESET, BASE + VX_COMMAND);
87 outw(C_INTR_LATCH, BASE + VX_COMMAND);
88 outw(SET_RD_0_MASK, BASE + VX_COMMAND);
89 outw(SET_INTR_MASK, BASE + VX_COMMAND);
90 outw(SET_RX_FILTER, BASE
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H A Dtlan.c234 static u32 BASE; variable
319 data = inl(BASE + TLAN_HOST_CMD);
321 outl(data, BASE + TLAN_HOST_CMD);
327 data = inl(BASE + TLAN_HOST_CMD);
329 outl(data, BASE + TLAN_HOST_CMD);
333 TLan_DioWrite32(BASE, (u16) i, 0);
340 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
344 outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
345 outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
349 outw(TLAN_NET_SIO, BASE
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H A Ddmfe.c234 static long int BASE; variable
287 unsigned long ioaddr = BASE;
419 outl(0, BASE + DCR7);
435 outl(0x1, BASE + DCR1);
436 outl(db->cr7_data, BASE + DCR7);
448 outl(DM910X_RESET, BASE + DCR0);
450 phy_write(BASE, db->phy_addr, 0, 0x8000, db->chip_id);
468 BASE = pci->ioaddr;
480 BASE = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
494 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(BASE,
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H A Dsundance.c251 /* FIXME: Move BASE to the private structure */
252 static u32 BASE; variable
308 outw(inw(BASE + MACCtrl0) | EnbFullDuplex,
309 BASE + MACCtrl0);
321 outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0,
322 BASE + MACCtrl0);
378 outl(virt_to_le32desc(&rx_ring[0]), BASE + RxListPtr);
387 outw(addr16, BASE + StationAddr);
389 outw(addr16, BASE + StationAddr + 2);
391 outw(addr16, BASE
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H A D3c595.h69 #define BASE (eth_nic_base) macro
119 #define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a
121 #define VX_STATUS 0x0e /* Read. BASE+0x0e is always status
123 #define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window
298 #define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS)
418 #define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND)
H A Dsmc9000.h136 #define BASE 2 macro
H A Dvia-velocity.c76 /* FIXME: Move BASE to the private structure */
77 static u32 BASE; variable
712 BASE = vptr->ioaddr;
720 (unsigned int) BASE );
H A Dsmc9000.c580 base_address_register = inw(ioaddr + BASE);
/vbox/include/iprt/cpp/
H A Dmtlist.h95 typedef RTCListBase<T, ITYPE, true> BASE; typedef in class:RTCMTList
106 RTCMTList(size_t cCapacity = BASE::kDefaultCapacity) argument
107 : BASE(cCapacity) {}
123 typedef RTCListBase<uint64_t, uint64_t, true> BASE; typedef in class:RTCMTList
134 RTCMTList(size_t cCapacity = BASE::kDefaultCapacity) argument
135 : BASE(cCapacity) {}
151 typedef RTCListBase<int64_t, int64_t, true> BASE; typedef in class:RTCMTList
162 RTCMTList(size_t cCapacity = BASE::kDefaultCapacity) argument
163 : BASE(cCapacity) {}
H A Dlist.h917 typedef RTCListBase<T, ITYPE, false> BASE;
928 RTCList(size_t cCapacity = BASE::kDefaultCapacity)
929 : BASE(cCapacity) {}
931 RTCList(const BASE &other)
932 : BASE(other) {}
948 typedef RTCListBase<uint64_t, uint64_t, false> BASE;
959 RTCList(size_t cCapacity = BASE::kDefaultCapacity)
960 : BASE(cCapacity) {}
976 typedef RTCListBase<int64_t, int64_t, false> BASE;
987 RTCList(size_t cCapacity = BASE
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/vbox/include/VBox/com/
H A Dlist.h48 typedef RTCListBase<T, ITYPE, MT> BASE; typedef in class:RTCList
59 RTCList(size_t cCapacity = BASE::kDefaultCapacity) argument
60 : BASE(cCapacity) {}
78 typedef RTCListBase<T, ITYPE, MT> BASE; typedef in class:RTCList
89 RTCList(size_t cCapacity = BASE::kDefaultCapacity) argument
90 : BASE(cCapacity) {}
108 typedef RTCListBase<T, ITYPE, MT> BASE; typedef in class:RTCList
119 RTCList(size_t cCapacity = BASE::kDefaultCapacity) argument
120 : BASE(cCapacity) {}
153 : BASE(othe
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H A Dmtlist.h47 typedef RTCListBase<T, ITYPE, MT> BASE; typedef in class:RTCMTList
58 RTCMTList(size_t cCapacity = BASE::kDefaultCapacity) argument
59 : BASE(cCapacity) {}
77 typedef RTCListBase<T, ITYPE, MT> BASE; typedef in class:RTCMTList
88 RTCMTList(size_t cCapacity = BASE::kDefaultCapacity) argument
89 : BASE(cCapacity) {}
107 typedef RTCListBase<T, ITYPE, MT> BASE; typedef in class:RTCMTList
118 RTCMTList(size_t cCapacity = BASE::kDefaultCapacity) argument
119 : BASE(cCapacity) {}
152 : BASE(othe
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/vbox/src/VBox/Devices/EFI/Firmware/BaseTools/Source/Python/UPT/Logger/
H A DStringTable.py207 ERR_INF_PARSER_MODULETYPE_INVALID = _("Drivers and applications are not allowed to have a MODULE_TYPE of \"BASE\". "
208 "Only libraries are permitted to a have a MODULE_TYPE of \"BASE\".")
267 "BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER SMM_CORE DXE_SMM_DRIVER DXE_RUNTIME_DRIVER "
/vbox/src/VBox/Main/webservice/jaxlibs/
H A Dresolver.jarMETA-INF/ META-INF/MANIFEST.MF com/ com/sun/ com/sun/org/ com/sun/org/apache/ ...
H A Djaxws-rt.jarMETA-INF/ META-INF/MANIFEST.MF META-INF/services/ com/ com/sun/ com/sun/xml/ ...
H A Djaxb-xjc.jarMETA-INF/ META-INF/MANIFEST.MF META-INF/maven/ META-INF/maven/com. ...

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