Lines Matching refs:BASE
234 static u32 BASE;
319 data = inl(BASE + TLAN_HOST_CMD);
321 outl(data, BASE + TLAN_HOST_CMD);
327 data = inl(BASE + TLAN_HOST_CMD);
329 outl(data, BASE + TLAN_HOST_CMD);
333 TLan_DioWrite32(BASE, (u16) i, 0);
340 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
344 outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
345 outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
349 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
350 addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
357 TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
365 TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
367 TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
370 TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
377 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
406 TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
411 TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
412 TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
454 TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
465 TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
473 sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
475 TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
481 outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
482 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
483 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
511 u16 host_int = inw(BASE + TLAN_HOST_INT);
516 outw(host_int, BASE + TLAN_HOST_INT);
545 outl(host_cmd, BASE + TLAN_HOST_CMD);
549 outl(host_cmd, BASE + TLAN_HOST_CMD);
551 DBG ( "AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM) );
552 DBG ( "PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT) );
590 u16 host_int = inw(BASE + TLAN_HOST_INT);
653 DBG ( "INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
657 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
658 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
673 DBG ( "INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
695 outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
703 outl(host_cmd, BASE + TLAN_HOST_CMD);
710 outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
716 outl(host_cmd, BASE + TLAN_HOST_CMD);
740 outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
771 tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
772 TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
777 TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
778 TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
800 BASE = pci->ioaddr;
827 err |= TLan_EeReadByte(BASE,
839 priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
845 data = inl(BASE + TLAN_HOST_CMD);
847 outw(data, BASE + TLAN_HOST_CMD);
1116 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1117 sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1119 TLan_MiiSync(BASE);
1125 TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1126 TLan_MiiSendData(BASE, 0x2, 2); /* Read ( 10b ) */
1127 TLan_MiiSendData(BASE, phy, 5); /* Device # */
1128 TLan_MiiSendData(BASE, reg, 5); /* Register # */
1266 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1267 sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1269 TLan_MiiSync(BASE);
1275 TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1276 TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
1277 TLan_MiiSendData(BASE, phy, 5); /* Device # */
1278 TLan_MiiSendData(BASE, reg, 5); /* Register # */
1280 TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
1281 TLan_MiiSendData(BASE, val, 16); /* Send Data */
1321 TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1325 TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1400 TLan_MiiSync(BASE);
1406 TLan_MiiSync(BASE);
1426 TLan_MiiSync(BASE);
1429 TLan_MiiSync(BASE);
1448 TLan_MiiSync(BASE);
1527 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1615 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);