Searched refs:simm13a (Results 1 - 4 of 4) sorted by relevance

/openjdk7/hotspot/src/cpu/sparc/vm/
H A Dassembler_sparc.inline.hpp80 inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); } argument
81 inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); } argument
109 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } argument
112 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { cti(); emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); } argument
120 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 1 argument
125 ldfsr( Register s1, int simm13a) argument
127 ldxfsr( Register s1, int simm13a) argument
130 ldc( Register s1, int simm13a, int crd) argument
132 lddc( Register s1, int simm13a, int crd) argument
134 ldcsr( Register s1, int simm13a, int crd) argument
137 ldsb( Register s1, int simm13a, Register d) argument
140 ldsh( Register s1, int simm13a, Register d) argument
142 ldsw( Register s1, int simm13a, Register d) argument
144 ldub( Register s1, int simm13a, Register d) argument
146 lduh( Register s1, int simm13a, Register d) argument
148 lduw( Register s1, int simm13a, Register d) argument
151 ldx( Register s1, int simm13a, Register d) argument
153 ldd( Register s1, int simm13a, Register d) argument
158 ld( Register s1, int simm13a, Register d) argument
161 ld( Register s1, int simm13a, Register d) argument
167 ld( Register s1, ByteSize simm13a, Register d) argument
169 ld( Register s1, ByteSize simm13a, Register d) argument
238 ldstub( Register s1, int simm13a, Register d) argument
242 prefetch(Register s1, int simm13a, PrefetchFcn f) argument
248 rett( Register s1, int simm13a, relocInfo::relocType rt) argument
260 stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) argument
269 stfsr( Register s1, int simm13a) argument
271 stxfsr( Register s1, int simm13a) argument
276 stb( Register d, Register s1, int simm13a) argument
278 sth( Register d, Register s1, int simm13a) argument
280 stw( Register d, Register s1, int simm13a) argument
284 stx( Register d, Register s1, int simm13a) argument
286 std( Register d, Register s1, int simm13a) argument
289 st( Register d, Register s1, int simm13a) argument
293 st( Register d, Register s1, ByteSize simm13a) argument
331 stc( int crd, Register s1, int simm13a) argument
333 stdc( int crd, Register s1, int simm13a) argument
335 stcsr( int crd, Register s1, int simm13a) argument
337 stdcq( int crd, Register s1, int simm13a) argument
348 swap( Register s1, int simm13a, Register d) argument
366 ld_ptr( Register s1, int simm13a, Register d ) argument
376 ld_ptr( Register s1, ByteSize simm13a, Register d ) argument
445 ld_long( Register s1, int simm13a, Register d ) argument
601 jmp( Register s1, int simm13a, RelocationHolder const& rspec ) argument
644 callr( Register s1, int simm13a, RelocationHolder const& rspec ) argument
837 clrb( Register s1, int simm13a) argument
838 clrh( Register s1, int simm13a) argument
839 clr( Register s1, int simm13a) argument
840 clrx( Register s1, int simm13a) argument
[all...]
H A Dassembler_sparc.hpp1233 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1234 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1239 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } argument
1241 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } argument
1243 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } argument
1302 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 1 argument
1304 sdiv( Register s1, int simm13a, Register d ) argument
1306 udivcc( Register s1, int simm13a, Register d ) argument
1308 sdivcc( Register s1, int simm13a, Register d ) argument
1423 ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) argument
1474 ldsba( Register s1, int simm13a, Register d ) argument
1476 ldsha( Register s1, int simm13a, Register d ) argument
1478 ldswa( Register s1, int simm13a, Register d ) argument
1480 lduba( Register s1, int simm13a, Register d ) argument
1482 lduha( Register s1, int simm13a, Register d ) argument
1484 lduwa( Register s1, int simm13a, Register d ) argument
1486 ldxa( Register s1, int simm13a, Register d ) argument
1488 ldda( Register s1, int simm13a, Register d ) argument
1498 ldstuba( Register s1, int simm13a, Register d ) argument
1503 and3( Register s1, int simm13a, Register d ) argument
1505 andcc( Register s1, int simm13a, Register d ) argument
1507 andn( Register s1, int simm13a, Register d ) argument
1510 andncc( Register s1, int simm13a, Register d ) argument
1512 or3( Register s1, int simm13a, Register d ) argument
1514 orcc( Register s1, int simm13a, Register d ) argument
1516 orn( Register s1, int simm13a, Register d ) argument
1518 orncc( Register s1, int simm13a, Register d ) argument
1520 xor3( Register s1, int simm13a, Register d ) argument
1522 xorcc( Register s1, int simm13a, Register d ) argument
1524 xnor( Register s1, int simm13a, Register d ) argument
1526 xnorcc( Register s1, int simm13a, Register d ) argument
1553 mulx( Register s1, int simm13a, Register d ) argument
1555 sdivx( Register s1, int simm13a, Register d ) argument
1557 udivx( Register s1, int simm13a, Register d ) argument
1562 umul( Register s1, int simm13a, Register d ) argument
1564 smul( Register s1, int simm13a, Register d ) argument
1566 umulcc( Register s1, int simm13a, Register d ) argument
1568 smulcc( Register s1, int simm13a, Register d ) argument
1573 mulscc( Register s1, int simm13a, Register d ) argument
1583 popc( int simm13a, Register d) argument
1590 prefetcha( Register s1, int simm13a, PrefetchFcn f ) argument
1613 save( Register s1, int simm13a, Register d ) argument
1620 restore( Register s1, int simm13a, Register d ) argument
1732 sub( Register s1, int simm13a, Register d ) argument
1738 subcc( Register s1, int simm13a, Register d ) argument
1740 subc( Register s1, int simm13a, Register d ) argument
1742 subccc( Register s1, int simm13a, Register d ) argument
1753 swapa( Register s1, int simm13a, Register d ) argument
1758 taddcc( Register s1, int simm13a, Register d ) argument
1760 taddcctv( Register s1, int simm13a, Register d ) argument
1765 tsubcc( Register s1, int simm13a, Register d ) argument
1767 tsubcctv( Register s1, int simm13a, Register d ) argument
1780 wrccr(Register s, int simm13a) argument
1788 wrasi(Register d, int simm13a) argument
2087 btst( int simm13a, Register s ) argument
2090 bset( int simm13a, Register s ) argument
2093 bclr( int simm13a, Register s ) argument
2096 btog( int simm13a, Register s ) argument
2132 mov( int simm13a, Register d) argument
[all...]
H A Dassembler_sparc.cpp779 void MacroAssembler::mult(Register s1, int simm13a, Register d) { argument
781 mulx (s1, simm13a, d);
783 smul (s1, simm13a, d);
2177 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c, argument
2180 if (is_simm(simm13a,5) && use_cbcond(L)) {
2181 Assembler::cbcond(c, icc, s1, simm13a, L);
2183 cmp(s1, simm13a);
2203 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c, argument
2206 if (is_simm(simm13a,5) && use_cbcond(L)) {
2207 Assembler::cbcond(c, ptr_cc, s1, simm13a,
4717 load_heap_oop(Register s1, int simm13a, Register d) argument
4741 store_heap_oop(Register d, Register s1, int simm13a) argument
[all...]
H A DnativeInst_sparc.hpp153 static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) { argument
154 return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13);

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