Searched refs:cbcond (Results 1 - 3 of 3) sorted by relevance

/openjdk7/hotspot/src/cpu/sparc/vm/
H A Dassembler_sparc.cpp2161 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
2168 Assembler::cbcond(c, icc, s1, s2, L);
2181 Assembler::cbcond(c, icc, s1, simm13a, L);
2194 Assembler::cbcond(c, ptr_cc, s1, s2, L);
2207 Assembler::cbcond(c, ptr_cc, s1, simm13a, L);
2220 Assembler::cbcond(zero, ptr_cc, s1, 0, L);
2230 Assembler::cbcond(notZero, ptr_cc, s1, 0, L);
2240 Assembler::cbcond(equal, icc, G0, G0, L);
H A Dassembler_sparc.inline.hpp102 inline void Assembler::cbcond(Condition c, CC cc, Register s1, Register s2, Label& L) { cti(); no_cbcond_before(); emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | rs2(s2)); } function in class:Assembler
103 inline void Assembler::cbcond(Condition c, CC cc, Register s1, int simm5, Label& L) { cti(); no_cbcond_before(); emit_data(op(branch_op) | cond_cbcond(c) | op2(bpr_op2) | branchcc(cc) | wdisp10(intptr_t(target(L)), intptr_t(pc())) | rs1(s1) | immed(true) | simm(simm5, 5)); } function in class:Assembler
H A Dassembler_sparc.hpp1060 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
1067 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
1183 // cbcond instruction should not be generated one after an other
1191 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
1252 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
1253 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
1942 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
1944 // ATTENTION: use these instructions with caution because cbcond instruction

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