Searched refs:pil (Results 1 - 25 of 56) sorted by relevance

123

/illumos-gate/usr/src/uts/sun4v/promif/
H A Dpromif_mon.c66 PIL_DECL(pil);
68 PIL_SET7(pil);
82 PIL_REST(pil);
93 PIL_DECL(pil);
95 PIL_SET7(pil);
140 PIL_REST(pil);
/illumos-gate/usr/src/psm/stand/boot/sparc/common/
H A Dsparcv9_subr.s227 rdpr %pil, %o1 ! get current pil
228 wrpr %o0, %pil
263 rdpr %pil, %o1 ! get current pil
267 wrpr %o0, %pil
269 mov %o1, %o0 ! return the old pil
/illumos-gate/usr/src/uts/i86pc/os/
H A Dintr.c284 * | | | softint pil too low | |
524 * The 'pil' is already set to the appropriate level for rp->r_trapno.
527 hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp) argument
534 ASSERT(pil > LOCK_LEVEL);
536 if (pil == CBE_HIGH_PIL) {
561 ASSERT(nestpil < pil);
591 mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
593 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
595 if (pil == 15) {
608 cpu->cpu_intr_actv |= (1 << pil);
623 hilevel_intr_epilog(struct cpu *cpu, uint_t pil, uint_t oldpil, uint_t vecnum) argument
704 intr_thread_prolog(struct cpu *cpu, caddr_t stackptr, uint_t pil) argument
775 uint_t pil, basespl; local
911 uint_t pil; local
946 uint_t pil; local
1053 uint_t pil, basespl; local
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/illumos-gate/usr/src/uts/i86pc/io/apix/
H A Dapix_intr.c227 apix_do_softint_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, argument
235 ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl);
237 atomic_and_32((uint32_t *)&mcpu->mcpu_softinfo.st_pending, ~(1 << pil));
239 mcpu->mcpu_pri = pil;
256 mcpu->intrstat[pil][0] += intrtime;
284 * Set bit for this pil in CPU's interrupt active bitmask.
286 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
287 cpu->cpu_intr_actv |= (1 << pil);
292 it->t_pil = (uchar_t)pil;
304 uint_t pil, basespl; local
403 apix_hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp) argument
486 uint_t mask, pil; local
605 apix_intr_thread_prolog(struct cpu *cpu, uint_t pil, caddr_t stackptr) argument
679 uint_t pil, basespl; local
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/illumos-gate/usr/src/uts/sun4/io/
H A Divintr.c184 add_ivintr(uint_t inum, uint_t pil, intrfunc intr_handler, argument
189 if (inum >= MAXIVNUM || pil > PIL_MAX)
202 if (iv_p->iv_pil == pil) {
215 new_iv_p->iv_pil = (ushort_t)pil;
229 rem_ivintr(uint_t inum, uint_t pil) argument
233 if (inum >= MAXIVNUM || pil > PIL_MAX)
240 if (iv_p->iv_pil == pil)
265 add_softintr(uint_t pil, softintrfunc intr_handler, caddr_t intr_arg1, argument
270 if (pil > PIL_MAX)
277 iv_p->iv_pil = (ushort_t)pil;
346 update_softint_pri(uint64_t softint_id, uint_t pil) argument
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/illumos-gate/usr/src/uts/sun4/sys/
H A Divintr.h75 * vector with unique pil basis, i.e, interrupts sharing the same ino and the
76 * same pil do share the same structure.
118 extern int add_ivintr(uint_t inum, uint_t pil, intrfunc intr_handler,
120 extern int rem_ivintr(uint_t inum, uint_t pil);
122 extern uint64_t add_softintr(uint_t pil, softintrfunc intr_handler,
126 extern int update_softint_pri(uint64_t softint_id, uint_t pil);
/illumos-gate/usr/src/boot/sys/boot/sparc64/loader/
H A Dlocore.S27 wrpr %g0, PIL_TICK - 1, %pil
/illumos-gate/usr/src/uts/sun4/ml/
H A Dinterrupt.s64 ! %g4 - pil
67 ! Grab the first or list head intr_vec_t off the intr_head[pil]
69 ! intr_head[pil] to next intr_vec_t on the list and clear softint
75 sll %g4, CPTRSHIFT, %g5 ! %g5 = offset to the pil entry
77 add %g6, %g5, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
78 ldn [%g6], %g2 ! %g2 = cpu->m_cpu.intr_head[pil]
94 stn %g3, [%g6] ! update cpu->m_cpu.intr_head[pil]
96 stn %g0, [%g5 + %g6] ! clear cpu->m_cpu.intr_tail[pil]
98 sll %g5, %g4, %g5 ! %g5 = 1 << pil
99 wr %g5, CLEAR_SOFTINT ! clear interrupt on this pil
[all...]
H A Dxc.s88 * %g4 - pil
96 rdpr %pil, %g4
/illumos-gate/usr/src/uts/sun4v/sys/
H A Dcnex.h49 uint32_t pil; /* PIL for device class */ member in struct:cnex_intr_map
H A Dmachsystm.h230 extern void intr_enqueue_req(uint_t pil, uint64_t inum);
231 extern void intr_dequeue_req(uint_t pil, uint64_t inum);
/illumos-gate/usr/src/uts/sun4/os/
H A Dintr.c334 no_ivintr(struct regs *rp, int inum, int pil) argument
337 cmn_err(CE_WARN, "invalid vector intr: number 0x%x, pil 0x%x",
338 inum, pil);
346 intr_dequeue_req(uint_t pil, uint64_t inum) argument
361 next = mcpu->intr_head[pil];
378 mcpu->intr_head[pil] = next_iv; /* head */
381 mcpu->intr_tail[pil] = prev; /* tail */
385 if (mcpu->intr_head[pil] == NULL) {
386 clr = 1 << pil;
387 if (pil
842 create_softint(uint_t pil, uint_t (*func)(caddr_t, caddr_t), caddr_t arg1) argument
[all...]
/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_ib.h57 * ih structure: one per every consumer of each ino and pil pair with interrupt
88 * ino_pil structure: one per each ino and pil pair with interrupt registered
91 ushort_t ipil_pil; /* pil for this ino */
113 ushort_t ino_lopil; /* lowest pil sharing ino */
114 ushort_t ino_claimed; /* pil bit masks, who claimed intr */
118 ushort_t ino_ipil_cntr; /* counter for pil sharing ino */
142 extern px_ino_pil_t *px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil);
145 uint_t pil, px_ih_t *ih_p);
158 devino_t ino, uint_t pil, uint_t new_intr_state,
H A Dpx_ib.c485 px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num, uint_t pil, px_ih_t *ih_p) argument
496 ipil_p->ipil_pil = pil;
507 if ((ino_p->ino_lopil == 0) || (ino_p->ino_lopil > pil))
508 ino_p->ino_lopil = pil;
517 ushort_t pil = ipil_p->ipil_pil; local
535 if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) {
536 for (next = ino_p->ino_ipil_p, pil = next->ipil_pil;
539 if (pil > next->ipil_pil)
540 pil = next->ipil_pil;
544 * Value stored in pil shoul
589 px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil) argument
807 px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum, devino_t ino, uint_t pil, uint_t new_intr_state, msiq_rec_type_t rec_type, msgcode_t msg_code) argument
[all...]
/illumos-gate/usr/src/uts/sparc/v9/ml/
H A Dsparcv9_subr.s76 rdpr %pil, %o1; /* get current PIL */ \
80 wrpr %g0, PIL_MAX, %pil; /* freeze CPU_BASE_SPL */ \
85 wrpr %g0, %o2, %pil; \
97 rdpr %pil, %o1; /* get current PIL */ \
101 wrpr %g0, level, %pil; /* use chose value */ \
114 rdpr %pil, %o1; /* get current PIL */ \
115 wrpr %g0, PIL_MAX, %pil; /* freeze CPU_BASE_SPL */ \
120 wrpr %g0, %o2, %pil; \
132 rdpr %pil, %o1; /* get current PIL */ \
133 wrpr %g0, level, %pil; \
[all...]
H A Dlock_prim.s263 * Sets pil to new_pil, grabs lp, stores old pil in *old_pil_addr.
288 rdpr %pil, %o3 ! %o3 = current pil
289 cmp %o3, %o1 ! is current pil high enough?
290 bl,a,pt %icc, 1f ! if not, write %pil in delay
291 wrpr %g0, %o1, %pil
298 sth %o3, [%o2] ! delay - save original pil
333 wrpr %g0, %o2, %pil
/illumos-gate/usr/src/cmd/mdb/sparc/mdb/
H A Dkvm_v9dep.c250 uint32_t pil; local
360 * which on sparcv9 is the %pil register's value.
362 if (mdb_tgt_readsym(t, MDB_TGT_AS_VIRT, &pil, sizeof (pil),
363 MDB_TGT_OBJ_EXEC, "panic_ipl") == sizeof (pil))
364 kregs[KREG_PIL] = pil;
/illumos-gate/usr/src/cmd/mdb/sparc/modules/intr/
H A Dintr.c46 uint32_t pil; member in struct:intr_info
250 info.pil = niumx_state.niumx_ihtable[i].ih_pri;
337 info.pil = ipil.ipil_pil;
439 info.pil = ipil.ipil_pil;
507 mdb_printf(" %4d\t", info.pil);
531 mdb_printf("Pil:\t\t%d\n", info.pil);
/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Dpci_ib.c539 ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil, ih_t *ih_p) argument
556 ino_p->ino_lopil = pil;
560 ipil_p->ipil_pil = pil;
571 if (ino_p->ino_lopil > pil)
572 ino_p->ino_lopil = pil;
582 ushort_t pil = ipil_p->ipil_pil; local
599 if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) {
600 for (next = ino_p->ino_ipil_p, pil = next->ipil_pil;
603 if (pil > next->ipil_pil)
604 pil
645 ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil) argument
[all...]
/illumos-gate/usr/src/uts/sun4u/sys/pci/
H A Dpci_ib.h100 * ih structure: one per every consumer of each ino and pil pair with interrupt
123 * ino_pil structure: one per each ino and pil pair with interrupt registered
153 ushort_t ino_claimed; /* pil bit masks, who claimed intr */
206 extern ib_ino_pil_t *ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil,
210 extern ib_ino_pil_t *ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil);
223 extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil,
/illumos-gate/usr/src/uts/sun4v/io/
H A Dcnex.c611 int rv, idx, pil; local
684 for (idx = 0, pil = PIL_3; idx < CNEX_MAX_DEVS; idx++) {
686 pil = cnex_class_to_intr[idx].pil;
692 if (add_ivintr(iinfo->icookie, pil, (intrfunc)cnex_intr_wrapper,
734 (void) rem_ivintr(iinfo->icookie, pil);
800 int rv, idx, pil; local
878 for (idx = 0, pil = PIL_3; idx < CNEX_MAX_DEVS; idx++) {
880 pil = cnex_class_to_intr[idx].pil;
[all...]
/illumos-gate/usr/src/uts/sun4v/ml/
H A Dmach_interrupt.s452 rdpr %pil, %g4
476 rdpr %pil, %g4
645 rdpr %pil, %g4
657 rdpr %pil, %g4
H A Dmach_locore.s385 * %g4 desired %pil (-1 means current %pil)
392 * %l6 curthread for user traps, %pil for priv traps
497 mov %g5, %l6 ! curthread if user trap, %pil if priv trap
509 ! setup pil
515 ! ASSERT(%g4 >= %pil).
517 rdpr %pil, %l0
527 ba 1f ! stay at the current %pil
531 wrpr %g0, %g4, %pil
656 rdpr %pil,
[all...]
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dmachsystm.h233 extern void intr_enqueue_req(uint_t pil, uint64_t inum);
234 extern void intr_dequeue_req(uint_t pil, uint64_t inum);
/illumos-gate/usr/src/uts/sun4u/ml/
H A Dmach_locore.s377 * %g4 desired %pil (-1 means current %pil)
384 * %l6 curthread for user traps, %pil for priv traps
475 mov %g5, %l6 ! curthread if user trap, %pil if priv trap
487 ! setup pil
493 ! ASSERT(%g4 >= %pil).
495 rdpr %pil, %l0
505 ba 1f ! stay at the current %pil
509 wrpr %g0, %g4, %pil
547 rdpr %pil,
[all...]

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