7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * CDDL HEADER START
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7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Common Development and Distribution License (the "License").
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * You may not use this file except in compliance with the License.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * or http://www.opensolaris.org/os/licensing.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * See the License for the specific language governing permissions
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * and limitations under the License.
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7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * If applicable, add the following below this CDDL HEADER, with the
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7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * information: Portions Copyright [yyyy] [name of copyright owner]
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * CDDL HEADER END
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesstatic void apix_post_hardint(int);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Insert an vector into the tail of the interrupt pending list
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_insert_pending_av(apix_impl_t *apixp, struct autovec *avp, int ipl)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Remove and return an vector from the head of hardware interrupt
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * pending list.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_remove_pending_av(apix_impl_t *apixp, int ipl)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (avp->av_vector != NULL && avp->av_prilevel < cpu->cpu_base_spl) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * If there is blocked higher level interrupts, return
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * NULL to quit handling of current IPL level.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases apixp->x_intr_pending |= (1 << avp->av_prilevel);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * add_pending_hardint:
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Add hardware interrupts to the interrupt pending list.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases apix_vector_t *vecp = apixp->x_vectbl[vector];
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * The MSI interrupt not supporting per-vector masking could
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * be triggered on a false vector as a result of rebinding
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * operation cannot programme MSI address & data atomically.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Add ISR of this interrupt to the pending list for such
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * suspicious interrupt.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases for (p = vecp->v_autovect; p != NULL; p = p->av_link) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases continue; /* skip freed entry */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* set pending at specified priority level */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases continue; /* already in the pending list */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* insert into pending list by it original IPL */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* last one of the linked list */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (prevp && ((prevp->av_flags & AV_PENTRY_LEVEL) != 0))
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases prevp->av_flags |= (vector & AV_PENTRY_VECTMASK);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Walk pending hardware interrupts at given priority level, invoking
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * each interrupt handler as we go.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases while ((av = apix_remove_pending_av(apixp, ipl)) != NULL) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases uchar_t vector = av->av_flags & AV_PENTRY_VECTMASK;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* Don't enable interrupts during x-calls */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases DTRACE_PROBE4(interrupt__start, dev_info_t *, dip,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases void *, intr, caddr_t, arg1, caddr_t, arg2);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases DTRACE_PROBE4(interrupt__complete, dev_info_t *, dip,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (av->av_ticksp && av->av_prilevel <= LOCK_LEVEL)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases atomic_add_64(av->av_ticksp, intr_get_time());
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* mark it as idle */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_do_softint_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases atomic_and_32((uint32_t *)&mcpu->mcpu_softinfo.st_pending, ~(1 << pil));
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Get set to run interrupt thread.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * There should always be an interrupt thread since we
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * allocate one for each level on the CPU.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* t_intr_start could be zero due to cpu_intr_swtch_enter. */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Note that the code in kcpc_overflow_intr -relies- on the
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * ordering of events here - in particular that t->t_lwp of
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * the interrupt thread is set to the pinned thread *before*
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * curthread is changed.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Push interrupted thread onto list from new thread.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Set the new thread as the current one.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Set interrupted thread's T_SP because if it is the idle thread,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * resume() may use that stack between threads.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Set bit for this pil in CPU's interrupt active bitmask.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Initialize thread priority level from intr_pri
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_do_softint_epilog(struct cpu *cpu, uint_t oldpil)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * If there is still an interrupted thread underneath this one
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * then the interrupt was never blocked and the return is
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * fairly simple. Otherwise it isn't.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Put thread back on the interrupt thread list.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * This was an interrupt thread, so set CPU's base SPL.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* mcpu->mcpu_pri = cpu->cpu_base_spl; */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /*NOTREACHED*/
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Dispatch a soft interrupt
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_dispatch_softint(uint_t oldpil, uint_t arg2)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases av_dispatch_softvect((int)cpu->cpu_thread->t_pil);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Must run softint_epilog() on the interrupt thread stack, since
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * there may not be a return from it if the interrupt thread blocked.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Deliver any softints the current interrupt priority allows.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Called with interrupts disabled.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases while ((pending = cpu->cpu_softinfo.st_pending) != 0) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (newipl <= oldipl || newipl <= cpu->cpu_base_spl)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases newsp = apix_do_softint_prolog(cpu, newipl, oldipl,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases switch_sp_and_call(newsp, apix_dispatch_softint, oldipl, 0);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * We have interrupted another high-level interrupt.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Load starting timestamp, compute interval, update
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * cumulative counter.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)];
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * See if we are interrupting a low-level interrupt thread.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * If so, account for its time slice only if its time stamp
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * is non-zero.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if ((t->t_flag & T_INTR_THREAD) != 0 && t->t_intr_start != 0) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* store starting timestamp in CPu structure for this IPL */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * To support reentrant level 15 interrupts, we maintain a
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * recursion count in the top half of cpu_intr_actv. Only
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * when this count hits zero do we clear the PIL 15 bit from
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * the lower half of cpu_intr_actv.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* clear pending ipl level bit */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_hilevel_intr_epilog(struct cpu *cpu, uint_t oldpil)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * To support reentrant level 15 interrupts, we maintain a
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * recursion count in the top half of cpu_intr_actv. Only
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * when this count hits zero do we clear the PIL 15 bit from
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * the lower half of cpu_intr_actv.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (--(*refcntp) == 0)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)];
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Check for lower-pil nested high-level interrupt beneath
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * current one. If so, place a starting timestamp in its
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * pil_high_start entry.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * find PIL of nested interrupt
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * (Another high-level interrupt is active below this one,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * so there is no need to check for an interrupt
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * thread. That will be done by the lowest priority
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * high-level interrupt active.)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Check to see if there is a low-level interrupt active.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * If so, place a starting timestamp in the thread
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Dispatch a hilevel interrupt (one above LOCK_LEVEL)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_dispatch_pending_hilevel(uint_t ipl, uint_t arg2)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_do_pending_hilevel(struct cpu *cpu, struct regs *rp)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases while ((pending = HILEVEL_PENDING(cpu)) != 0) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT(newipl > LOCK_LEVEL && newipl > cpu->cpu_base_spl);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * High priority interrupts run on this cpu's interrupt stack.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (apix_hilevel_intr_prolog(cpu, newipl, oldipl, rp) == 0) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases switch_sp_and_call(newsp, apix_dispatch_pending_hilevel,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases } else { /* already on the interrupt stack */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases (void) apix_hilevel_intr_epilog(cpu, oldipl);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Get an interrupt thread and swith to it. It's called from do_interrupt().
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * The IF flag is cleared and thus all maskable interrupts are blocked at
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * the time of calling.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_intr_thread_prolog(struct cpu *cpu, uint_t pil, caddr_t stackptr)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Get set to run interrupt thread.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * There should always be an interrupt thread since we
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * allocate one for each level on the CPU.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* t_intr_start could be zero due to cpu_intr_swtch_enter. */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Push interrupted thread onto list from new thread.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Set the new thread as the current one.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Set interrupted thread's T_SP because if it is the idle thread,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * resume() may use that stack between threads.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases t->t_sp = (uintptr_t)stackptr; /* mark stack in curthread for resume */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Note that the code in kcpc_overflow_intr -relies- on the
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * ordering of events here - in particular that t->t_lwp of
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * the interrupt thread is set to the pinned thread *before*
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * curthread is changed.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * (threads on the interrupt thread free list could have state
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * preset to TS_ONPROC, but it helps in debugging if
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * they're TS_FREE.)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Initialize thread priority level from intr_pri
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_intr_thread_epilog(struct cpu *cpu, uint_t oldpil)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * If there is still an interrupted thread underneath this one
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * then the interrupt was never blocked and the return is
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * fairly simple. Otherwise it isn't.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * The interrupted thread is no longer pinned underneath
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * the interrupt thread. This means the interrupt must
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * have blocked, and the interrupted thread has been
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * unpinned, and has probably been running around the
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * system for a while.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Since there is no longer a thread under this one, put
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * this interrupt thread back on the CPU's free list and
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * resume the idle thread which will dispatch the next
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * thread to run.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Put thread back on the interrupt thread list.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * This was an interrupt thread, so set CPU's base SPL.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Return interrupt thread to pool
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /*NOTREACHED*/
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Return interrupt thread to the pool
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_dispatch_pending_hardint(uint_t oldpil, uint_t arg2)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases apix_dispatch_pending_autovect((int)cpu->cpu_thread->t_pil);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Must run intr_thread_epilog() on the interrupt thread stack, since
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * there may not be a return from it if the interrupt thread blocked.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_do_pending_hardint(struct cpu *cpu, struct regs *rp)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases while ((pending = LOWLEVEL_PENDING(cpu)) != 0) {
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (newipl <= oldipl || newipl <= cpu->cpu_base_spl)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Run this interrupt in a separate thread.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases newsp = apix_intr_thread_prolog(cpu, newipl, (caddr_t)rp);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases switch_sp_and_call(newsp, apix_dispatch_pending_hardint,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Unmask level triggered interrupts
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases apix_vector_t *vecp = xv_vector(psm_get_cpu_id(), vector);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases ASSERT(vecp->v_type == APIX_TYPE_FIXED && apic_level_intr[irqno]);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases apix_vector_t *vecp = xv_vector(cpu->cpu_id, vector);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases (avp = vecp->v_autovect) == NULL || avp->av_vector == NULL)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases DTRACE_PROBE4(interrupt__start, dev_info_t *, dip,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases void *, intr, caddr_t, arg1, caddr_t, arg2);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases DTRACE_PROBE4(interrupt__complete, dev_info_t *, dip,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_dispatch_hilevel(uint_t vector, uint_t arg2)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_dispatch_lowlevel(uint_t vector, uint_t oldipl)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Must run intr_thread_epilog() on the interrupt thread stack, since
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * there may not be a return from it if the interrupt thread blocked.
636dfb4b6ac0749387c883053011a3afb4b4893bJerry Jelinek * Interrupt service routine, called with interrupts disabled.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayasesapix_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases int vector = rp->r_trapno, newipl, oldipl = cpu->cpu_pri, ret;
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases#endif /* TRAPTRACE */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * If it's a softint go do it now.
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * It might be the case that when an interrupt is triggered,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * the spl is raised to high by splhigh(). Later when do_splx()
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * is called to restore the spl, both hardware and software
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * interrupt pending flags are check and an SOFTINT is faked
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * accordingly.
636dfb4b6ac0749387c883053011a3afb4b4893bJerry Jelinek * Send EOI to local APIC
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases newipl = (*setlvl)(oldipl, (int *)&rp->r_trapno);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases#endif /* TRAPTRACE */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Bail if it is a spurious interrupt
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases#endif /* TRAPTRACE */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Direct dispatch for IPI, MSI, MSI-X
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (vecp && vecp->v_type != APIX_TYPE_FIXED &&
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (apix_hilevel_intr_prolog(cpu, newipl, oldipl, rp)
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases switch_sp_and_call(newsp, apix_dispatch_hilevel,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases (void) apix_hilevel_intr_epilog(cpu, oldipl);
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases newsp = apix_intr_thread_prolog(cpu, newipl,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases switch_sp_and_call(newsp, apix_dispatch_lowlevel,
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases /* Add to per-pil pending queue */
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases if (newipl <= MAX(oldipl, cpu->cpu_base_spl) ||
7ff178cd8db129d385d3177eb20744d3b6efc59bJimmy Vetayases * Deliver any pending soft interrupts.