H A D | bnxe_clc.c | 2024 /* Use lane 1 (of lanes 0-3) */ 2033 /* Use lane 1 (of lanes 0-3) */ 3514 u8 lane = 0; local 3546 lane = (port<<1) + path; 3561 lane = path << 1 ; 3564 return lane; 3583 /* In Dual-lane mode, two lanes are joined together, 3835 u8 lane = elink_get_warpcore_lane(phy, params); local 3842 lane; 3902 * i.e. reset the lane (i 4019 u16 lane = elink_get_warpcore_lane(phy, params); local 4032 u16 lane, i, cl72_ctrl, an_adv = 0, val; local 4186 u16 val16, i, lane; local 4254 u16 misc1_val, tap_val, tx_driver_val, lane, val; local 4420 elink_warpcore_set_20G_DXGXS(struct elink_dev *cb, struct elink_phy *phy, u16 lane) argument 4580 elink_warpcore_clear_regs(struct elink_phy *phy, struct elink_params *params, u16 lane) argument 4676 u16 gp2_status_reg0, lane; local 4702 u16 lane = elink_get_warpcore_lane(phy, params); local 4745 u16 lane = elink_get_warpcore_lane(phy, params); local 4789 u16 lane = elink_get_warpcore_lane(phy, params); local 4899 u16 val16, lane; local 4957 u32 lane; local 5171 u16 lane, val; local 5208 u16 lane, val; local 6341 u8 lane; local 7161 u8 lane = elink_get_warpcore_lane(int_phy, params); local 9467 u8 lane = elink_get_warpcore_lane(phy, params); local 15127 u16 base_page, next_page, not_kr2_device, lane; local 15527 u8 lane = elink_get_warpcore_lane(phy, params); local [all...] |