Searched refs:cfgh (Results 1 - 10 of 10) sorted by relevance

/illumos-gate/usr/src/uts/common/io/xge/drv/
H A Dxge_osdep.h298 #define xge_os_pci_read8(pdev, cfgh, where, val) \
299 (*(val) = pci_config_get8(cfgh, where))
301 #define xge_os_pci_write8(pdev, cfgh, where, val) \
302 pci_config_put8(cfgh, where, val)
304 #define xge_os_pci_read16(pdev, cfgh, where, val) \
305 (*(val) = pci_config_get16(cfgh, where))
307 #define xge_os_pci_write16(pdev, cfgh, where, val) \
308 pci_config_put16(cfgh, where, val)
310 #define xge_os_pci_read32(pdev, cfgh, where, val) \
311 (*(val) = pci_config_get32(cfgh, wher
[all...]
H A Dxge.c1147 ret = pci_config_setup(dev_info, &attr.cfgh);
1285 pci_config_teardown(&attr.cfgh);
1376 pci_config_teardown(&attr->cfgh);
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_hcall.s126 hv_niu_cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
132 hv_niu_cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
138 hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
144 hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
150 hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
569 * hv_niu__cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
580 * hv_niu__cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx,
594 * hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
605 * hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx,
619 * hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_
[all...]
/illumos-gate/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-mgmt.c59 xge_os_pci_read16(hldev->pdev, hldev->cfgh,
63 xge_os_pci_read16(hldev->pdev, hldev->cfgh,
67 xge_os_pci_read16(hldev->pdev, hldev->cfgh,
71 xge_os_pci_read16(hldev->pdev, hldev->cfgh,
75 xge_os_pci_read8(hldev->pdev, hldev->cfgh,
590 xge_os_pci_read8(hldev->pdev, hldev->cfgh, offset, (u8*)value);
592 xge_os_pci_read16(hldev->pdev, hldev->cfgh, offset,
595 xge_os_pci_read32(hldev->pdev, hldev->cfgh, offset, value);
704 xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4,
1447 xge_os_pci_read8(hldev->pdev, hldev->cfgh,
[all...]
H A Dxgehal-device.c216 xge_os_pci_read16(hldev->pdev,hldev->cfgh,
246 xge_os_pci_read16(hldev->pdev, hldev->cfgh,
567 xge_os_pci_read16(hldev->pdev, hldev->cfgh,
570 xge_os_pci_write16(hldev->pdev, hldev->cfgh,
586 xge_os_pci_read16(hldev->pdev, hldev->cfgh,
594 xge_os_pci_write16(hldev->pdev, hldev->cfgh,
2192 xge_os_pci_read16(hldev->pdev,hldev->cfgh,
2195 xge_os_pci_read8(hldev->pdev,hldev->cfgh,
2206 xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4,
2211 xge_os_pci_read16(hldev->pdev, hldev->cfgh,
[all...]
/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-device.h89 * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
103 pci_cfg_h cfgh; member in struct:xge_hal_device_attr_t
336 pci_cfg_h cfgh; member in struct:__anon6599
/illumos-gate/usr/src/uts/common/io/iwi/
H A Dipw2200.c291 ddi_acc_handle_t cfgh; local
300 0, 0, &ipw2200_csr_accattr, &cfgh);
307 ddi_put8(cfgh, (uint8_t *)(regs + 0x41), 0);
308 sc->sc_vendor = ddi_get16(cfgh,
310 sc->sc_device = ddi_get16(cfgh,
312 sc->sc_subven = ddi_get16(cfgh,
314 sc->sc_subdev = ddi_get16(cfgh,
321 ddi_regs_map_free(&cfgh);
/illumos-gate/usr/src/uts/common/io/ipw/
H A Dipw2100.c257 ddi_acc_handle_t cfgh; local
294 0, 0, &ipw2100_csr_accattr, &cfgh);
300 ddi_put8(cfgh, (uint8_t *)(regs + 0x41), 0);
301 ddi_regs_map_free(&cfgh);
/illumos-gate/usr/src/uts/sun4v/io/
H A Dvsw.c1646 uint64_t cfgh; local
1718 if (md_get_prop_val(mdp, listp[i], "cfg-handle", &cfgh) != 0) {
1725 if (inst != cfgh)
H A Dvnet_gen.c1294 uint64_t cfgh; local
1338 if (md_get_prop_val(mdp, listp[i], "cfg-handle", &cfgh) != 0) {
1343 if (vgenp->regprop != cfgh)

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