a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER START
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The contents of this file are subject to the terms of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Common Development and Distribution License (the "License").
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You may not use this file except in compliance with the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * or http://www.opensolaris.org/os/licensing.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See the License for the specific language governing permissions
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and limitations under the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * When distributing Covered Code, include this CDDL HEADER in each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * If applicable, add the following below this CDDL HEADER, with the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * fields enclosed by brackets "[]" replaced with your own identifying
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information: Portions Copyright [yyyy] [name of copyright owner]
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER END
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Copyright (c) 2002-2006 Neterion, Inc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
193974072f41a843678abf5f61979c748687e66bSherry Moore/*
193974072f41a843678abf5f61979c748687e66bSherry Moore * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
193974072f41a843678abf5f61979c748687e66bSherry Moore * Use is subject to license terms.
193974072f41a843678abf5f61979c748687e66bSherry Moore */
193974072f41a843678abf5f61979c748687e66bSherry Moore
a23fd118e437af0a7877dd313db8fdaa3537c675yl#ifndef XGE_HAL_DEVICE_H
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEVICE_H
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xge-os-pal.h"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xge-queue.h"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xgehal-event.h"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xgehal-config.h"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xgehal-regs.h"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xgehal-channel.h"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xgehal-stats.h"
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#include "xgehal-ring.h"
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__EXTERN_BEGIN_DECLS
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_VPD_LENGTH 80
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_CARD_XENA_VPD_ADDR 0x50
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_CARD_HERC_VPD_ADDR 0x80
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_VPD_READ_COMPLETE 0x80
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_VPD_BUFFER_SIZE 128
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MAGIC 0x12345678
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEAD 0xDEADDEAD
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DUMP_BUF_SIZE 0x4000
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_LRO_MAX_BUCKETS 32
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * enum xge_hal_card_e - Xframe adapter type.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_CARD_UNKNOWN: Unknown device.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_CARD_XENA: Xframe I device.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Enumerates Xframe adapter types. The corresponding PCI device
a23fd118e437af0a7877dd313db8fdaa3537c675yl * IDs are listed in the file xgehal-defs.h.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (See XGE_PCI_DEVICE_ID_XENA_1, etc.)
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_check_id().
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef enum xge_hal_card_e {
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_CARD_UNKNOWN = 0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_CARD_XENA = 1,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_CARD_HERC = 2,
7eced415e5dd557aef2d78483b5a7785f0e13670xw XGE_HAL_CARD_TITAN = 3,
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xge_hal_card_e;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_device_attr_t - Device memory spaces.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (Linux and the rest.)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @regh1: BAR1 mapped memory handle. Same comment as above.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @bar0: BAR0 virtual address.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @bar1: BAR1 virtual address.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @irqh: IRQ handle (Solaris).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @pdev: PCI device object.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
a23fd118e437af0a7877dd313db8fdaa3537c675yl * mapped memories. Also, includes a pointer to OS-specific PCI device object.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct xge_hal_device_attr_t {
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_reg_h regh0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_reg_h regh1;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_reg_h regh2;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *bar1;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *bar2;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_irq_h irqh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_cfg_h cfgh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_dev_h pdev;
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xge_hal_device_attr_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * enum xge_hal_device_link_state_e - Link state enumeration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_LINK_NONE: Invalid link state.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_LINK_DOWN: Link is down.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_LINK_UP: Link is up.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef enum xge_hal_device_link_state_e {
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_LINK_NONE,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_LINK_DOWN,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_LINK_UP
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xge_hal_device_link_state_e;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef enum xge_hal_pci_mode_e {
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_33MHZ_MODE = 0x0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_66MHZ_MODE = 0x1,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M1_RESERVED = 0x8,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M1_66MHZ_NS = 0xA,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M1_100MHZ_NS = 0xB,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M1_133MHZ_NS = 0xC,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_M2_RESERVED = 0xD,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_533_RESERVED = 0xE,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BASIC_MODE = 0x10,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCIX_BASIC_MODE = 0x11,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_INVALID_MODE = 0x12,
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xge_hal_pci_mode_e;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef enum xge_hal_pci_bus_frequency_e {
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200,
7eced415e5dd557aef2d78483b5a7785f0e13670xw XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xge_hal_pci_bus_frequency_e;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * enum xge_hal_pci_bus_width_e - PCI bus width enumeration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef enum xge_hal_pci_bus_width_e {
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_WIDTH_64BIT = 0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_WIDTH_32BIT = 1,
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2,
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xge_hal_pci_bus_width_e;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined (XGE_HAL_CONFIG_LRO)
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define IP_TOTAL_LENGTH_OFFSET 2
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define IP_FAST_PATH_HDR_MASK 0x45
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_FAST_PATH_HDR_MASK1 0x50
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_FAST_PATH_HDR_MASK2 0x10
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_FAST_PATH_HDR_MASK3 0x18
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define IP_SOURCE_ADDRESS_OFFSET 12
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define IP_DESTINATION_ADDRESS_OFFSET 16
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_DESTINATION_PORT_OFFSET 2
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_SOURCE_PORT_OFFSET 0
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_DATA_OFFSET_OFFSET 12
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_WINDOW_OFFSET 14
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_SEQUENCE_NUMBER_OFFSET 4
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct tcplro {
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 source;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 dest;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 seq;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 ack_seq;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 doff_res;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 ctrl;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 window;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 check;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 urg_ptr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl} tcplro_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct iplro {
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 version_ihl;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 tos;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 tot_len;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 id;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 frag_off;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 ttl;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 protocol;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 check;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 saddr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 daddr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl /*The options start here. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl} iplro_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
a23fd118e437af0a7877dd313db8fdaa3537c675yl * LRO object, one per each LRO session.
a23fd118e437af0a7877dd313db8fdaa3537c675yl*/
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct lro {
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* non-linear: contains scatter-gather list of
a23fd118e437af0a7877dd313db8fdaa3537c675yl xframe-mapped received buffers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl OS_NETSTACK_BUF os_buf;
a23fd118e437af0a7877dd313db8fdaa3537c675yl OS_NETSTACK_BUF os_buf_end;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* link layer header of the first frame;
a23fd118e437af0a7877dd313db8fdaa3537c675yl remains intack throughout the processing */
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 *ll_hdr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* IP header - gets _collapsed_ */
a23fd118e437af0a7877dd313db8fdaa3537c675yl iplro_t *ip_hdr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* transport header - gets _collapsed_ */
a23fd118e437af0a7877dd313db8fdaa3537c675yl tcplro_t *tcp_hdr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Next tcp sequence number */
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 tcp_next_seq_num;
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Current tcp seq & ack */
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 tcp_seq_num;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 tcp_ack_num;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* total number of accumulated (so far) frames */
a23fd118e437af0a7877dd313db8fdaa3537c675yl int sg_num;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* total data length */
a23fd118e437af0a7877dd313db8fdaa3537c675yl int total_length;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* receive side hash value, available from Hercules */
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 rth_value;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* In use */
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 in_use;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Total length of the fragments clubbed with the inital frame */
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 frags_len;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl /* LRO frame contains time stamp, if (ts_off != -1) */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int ts_off;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl} lro_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_spdm_entry_t
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Represents a single spdm entry in the SPDM table.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct xge_hal_spdm_entry_t {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ipaddr_t src_ip;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ipaddr_t dst_ip;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 jhash_value;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 l4_sp;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 l4_dp;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 spdm_entry;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 in_use;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 is_tcp;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 is_ipv4;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 tgt_queue;
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xge_hal_spdm_entry_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw#if defined(XGE_HAL_CONFIG_LRO)
7eced415e5dd557aef2d78483b5a7785f0e13670xwtypedef struct {
7eced415e5dd557aef2d78483b5a7785f0e13670xw lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS];
7eced415e5dd557aef2d78483b5a7785f0e13670xw int lro_next_idx;
7eced415e5dd557aef2d78483b5a7785f0e13670xw lro_t *lro_recent;
7eced415e5dd557aef2d78483b5a7785f0e13670xw} xge_hal_lro_desc_t;
7eced415e5dd557aef2d78483b5a7785f0e13670xw#endif
8347601bcb0a439f6e50fc36b4039a73d08700e1yl/*
7eced415e5dd557aef2d78483b5a7785f0e13670xw * xge_hal_vpd_data_t
7eced415e5dd557aef2d78483b5a7785f0e13670xw *
7eced415e5dd557aef2d78483b5a7785f0e13670xw * Represents vpd capabilty structure
8347601bcb0a439f6e50fc36b4039a73d08700e1yl */
7eced415e5dd557aef2d78483b5a7785f0e13670xwtypedef struct xge_hal_vpd_data_t {
7eced415e5dd557aef2d78483b5a7785f0e13670xw u8 product_name[XGE_HAL_VPD_LENGTH];
7eced415e5dd557aef2d78483b5a7785f0e13670xw u8 serial_num[XGE_HAL_VPD_LENGTH];
7eced415e5dd557aef2d78483b5a7785f0e13670xw} xge_hal_vpd_data_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_t
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * HAL device object. Represents Xframe.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
8347601bcb0a439f6e50fc36b4039a73d08700e1yl unsigned int magic;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_reg_h regh0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_reg_h regh1;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_reg_h regh2;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *isrbar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *bar1;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *bar2;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_irq_h irqh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_cfg_h cfgh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl pci_dev_h pdev;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_config_t pci_config_space;
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_pci_config_t pci_config_space_bios;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_config_t config;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_list_t free_channels;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_list_t fifo_channels;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_list_t ring_channels;
a23fd118e437af0a7877dd313db8fdaa3537c675yl volatile int is_initialized;
a23fd118e437af0a7877dd313db8fdaa3537c675yl volatile int terminating;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_stats_t stats;
a23fd118e437af0a7877dd313db8fdaa3537c675yl macaddr_t macaddr[1];
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_queue_h queueh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl volatile int mcast_refcnt;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int is_promisc;
a23fd118e437af0a7877dd313db8fdaa3537c675yl volatile xge_hal_device_link_state_e link_state;
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *upper_layer_info;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_attr_t orig_attr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 device_id;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 revision;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int msi_enabled;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int hw_is_initialized;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 inject_serr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 inject_ecc;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 inject_bad_tcode;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int inject_bad_tcode_for_chan_type;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int reset_needed_after_close;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int tti_enabled;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM];
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int bimodal_timer_val_us;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int bimodal_urange_a_en;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int bimodal_intr_cnt;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *spdm_mem_base;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 spdm_max_entries;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_spdm_entry_t **spdm_table;
a23fd118e437af0a7877dd313db8fdaa3537c675yl spinlock_t spdm_lock;
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_HAL_CONFIG_LRO)
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM];
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl spinlock_t xena_post_lock;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl /* bimodal workload stats */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int irq_workload_rxd[XGE_HAL_MAX_RING_NUM];
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM];
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM];
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM];
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM];
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM];
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int mtu_first_time_set;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 rxufca_lbolt;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 rxufca_lbolt_time;
a23fd118e437af0a7877dd313db8fdaa3537c675yl u64 rxufca_intr_thres;
a23fd118e437af0a7877dd313db8fdaa3537c675yl char* dump_buf;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_mode_e pci_mode;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bus_frequency_e bus_frequency;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bus_width_e bus_width;
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_vpd_data_t vpd_data;
a23fd118e437af0a7877dd313db8fdaa3537c675yl volatile int in_poll;
7eced415e5dd557aef2d78483b5a7785f0e13670xw u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR];
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xge_hal_device_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* ========================== PRIVATE API ================================= */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwvoid
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_device_event_queued(void *data, int event_type);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_device_set_swapper(xge_hal_device_t *hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_device_rth_it_configure(xge_hal_device_t *hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_device_rth_spdm_configure(xge_hal_device_t *hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line,
7eced415e5dd557aef2d78483b5a7785f0e13670xw u16 spdm_entry, u64 *spdm_line_val);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val,
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *addr);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
a23fd118e437af0a7877dd313db8fdaa3537c675yl void *addr);
7eced415e5dd557aef2d78483b5a7785f0e13670xwvoid __hal_device_get_vpd_data(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
a23fd118e437af0a7877dd313db8fdaa3537c675yl int max_millis);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_rts_mac_configure(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_device_rts_qos_configure(xge_hal_device_t *hldev);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_device_rts_port_configure(xge_hal_device_t *hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_device_rti_configure(xge_hal_device_t *hldev, int runtime);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwvoid
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwvoid
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_device_msix_intr_endis(xge_hal_device_t *hldev,
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_channel_t *channel, int flag);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* =========================== PUBLIC API ================================= */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylunsigned int
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_fix_time_ival_herc(xge_hal_device_t *hldev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl unsigned int time_ival);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable,
a23fd118e437af0a7877dd313db8fdaa3537c675yl u32 itable_size);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type,
a23fd118e437af0a7877dd313db8fdaa3537c675yl u16 bucket_size);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_rts_rth_init(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_rts_rth_clr(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_rts_rth_start(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_rts_rth_stop(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwint xge_hal_reinitialize_hw(xge_hal_device_t * hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl/**
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * xge_hal_device_rti_reconfigure
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @hldev: Hal Device
8347601bcb0a439f6e50fc36b4039a73d08700e1yl */
8347601bcb0a439f6e50fc36b4039a73d08700e1ylstatic inline xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_device_rti_reconfigure(xge_hal_device_t *hldev)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl{
8347601bcb0a439f6e50fc36b4039a73d08700e1yl return __hal_device_rti_configure(hldev, 1);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw/**
7eced415e5dd557aef2d78483b5a7785f0e13670xw * xge_hal_device_rts_port_reconfigure
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @hldev: Hal Device
7eced415e5dd557aef2d78483b5a7785f0e13670xw */
7eced415e5dd557aef2d78483b5a7785f0e13670xwstatic inline xge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev)
7eced415e5dd557aef2d78483b5a7785f0e13670xw{
7eced415e5dd557aef2d78483b5a7785f0e13670xw return __hal_device_rts_port_configure(hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw}
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_is_initialized - Returns 0 if device is not
a23fd118e437af0a7877dd313db8fdaa3537c675yl * initialized, non-zero otherwise.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device handle.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns 0 if device is not initialized, non-zero otherwise.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline int
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_is_initialized(xge_hal_device_h devh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl return ((xge_hal_device_t*)devh)->is_initialized;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device handle.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline int
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_in_poll(xge_hal_device_h devh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl return ((xge_hal_device_t*)devh)->in_poll;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_inject_ecc - Inject ECC error.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device, pointer to xge_hal_device_t structure.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @err_reg: Contains the error register.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * This function is used to inject ECC error into the driver flow.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * This facility can be used to test the driver flow in the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * case of ECC error is reported by the firmware.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns: void
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_inject_serr(),
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_inject_bad_tcode()
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((xge_hal_device_t*)devh)->inject_ecc = err_reg;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_inject_serr - Inject SERR error.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device, pointer to xge_hal_device_t structure.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @err_reg: Contains the error register.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * This function is used to inject SERR error into the driver flow.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * This facility can be used to test the driver flow in the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * case of SERR error is reported by firmware.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns: void
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_inject_ecc(),
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_inject_bad_tcode()
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((xge_hal_device_t*)devh)->inject_serr = err_reg;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_inject_bad_tcode - Inject Bad transfer code.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device, pointer to xge_hal_device_t structure.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @chan_type: Channel type (fifo/ring).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @t_code: Transfer code.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * This function is used to inject bad (Tx/Rx Data)transfer code
a23fd118e437af0a7877dd313db8fdaa3537c675yl * into the driver flow.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * This facility can be used to test the driver flow in the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * case of bad transfer code reported by firmware for a Tx/Rx data
a23fd118e437af0a7877dd313db8fdaa3537c675yl * transfer.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns: void
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr()
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type;
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_msi_enable(xge_hal_device_h devh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_msi_mode - Is MSI enabled?
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device handle.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns 0 if MSI is enabled for the specified device,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * non-zero otherwise.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline int
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_msi_mode(xge_hal_device_h devh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl return ((xge_hal_device_t*)devh)->msi_enabled;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_queue - Get per-device event queue.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device handle.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns: event queue associated with the specified HAL device.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline xge_queue_h
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_queue (xge_hal_device_h devh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl return ((xge_hal_device_t*)devh)->queueh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_attr - Get original (user-specified) device
a23fd118e437af0a7877dd313db8fdaa3537c675yl * attributes.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device handle.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns: original (user-specified) device attributes.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline xge_hal_device_attr_t*
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_attr(xge_hal_device_h devh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl return &((xge_hal_device_t*)devh)->orig_attr;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_private_set - Set ULD context.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device handle.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @data: pointer to ULD context
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Use HAL device to set upper-layer driver (ULD) context.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_from_private(), xge_hal_device_private()
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_private_set(xge_hal_device_h devh, void *data)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl ((xge_hal_device_t*)devh)->upper_layer_info = data;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_private - Get ULD context.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @devh: HAL device handle.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Use HAL device to get upper-layer driver (ULD) context.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns: ULD context.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_from_private(), xge_hal_device_private_set()
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline void*
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_private(xge_hal_device_h devh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl return ((xge_hal_device_t*)devh)->upper_layer_info;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_from_private - Get HAL device object from private.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @info_ptr: ULD context.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Use ULD context to get HAL device.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns: Device handle.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_private(), xge_hal_device_private_set()
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline xge_hal_device_h
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_from_private(void *info_ptr)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
7eced415e5dd557aef2d78483b5a7785f0e13670xw return xge_container_of((void ** ) info_ptr, xge_hal_device_t,
a23fd118e437af0a7877dd313db8fdaa3537c675yl upper_layer_info);
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/**
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_mtu_check - check MTU value for ranges
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @hldev: the device
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @new_mtu: new MTU value to check
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Will do sanity check for new MTU value.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Returns: XGE_HAL_OK - success.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_mtu_set()
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline xge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu)
a23fd118e437af0a7877dd313db8fdaa3537c675yl{
a23fd118e437af0a7877dd313db8fdaa3537c675yl if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl return XGE_HAL_ERR_INVALID_MTU_SIZE;
a23fd118e437af0a7877dd313db8fdaa3537c675yl }
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl return XGE_HAL_OK;
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_bcast_enable(xge_hal_device_h devh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_bcast_disable(xge_hal_device_h devh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_terminating(xge_hal_device_h devh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_attr_t *attr, xge_hal_device_config_t *config);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_terminate(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl int index, macaddr_t *macaddr);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl int index, macaddr_t macaddr);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev,
7eced415e5dd557aef2d78483b5a7785f0e13670xw int index);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675ylint xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_intr_enable(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_intr_disable(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_promisc_enable(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_promisc_disable(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 t_code);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_link_state_e *ls);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us,
a23fd118e437af0a7877dd313db8fdaa3537c675yl int one_shot);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_hal_device_poll(xge_hal_device_h devh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylint xge_hal_device_is_slot_freeze(xge_hal_device_h devh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
193974072f41a843678abf5f61979c748687e66bSherry Moorevoid xge_hal_device_quiesce(xge_hal_device_t *hldev, xge_hal_device_h devh);
193974072f41a843678abf5f61979c748687e66bSherry Moore
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bus_frequency_e *bus_frequency,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bus_width_e *bus_width);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 is_tcp, u8 is_ipv4, u8 tgt_queue);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
a23fd118e437af0a7877dd313db8fdaa3537c675yl u8 is_tcp, u8 is_ipv4);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_device_rts_section_enable(xge_hal_device_h devh, int index);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylint
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_is_closed (xge_hal_device_h devh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw/* private functions, don't use them in ULD */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwvoid __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwu64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* Some function protoypes for MSI implementation. */
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi,
7eced415e5dd557aef2d78483b5a7785f0e13670xw u32 msg_val);
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_mask_msi(xge_hal_device_t *hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_unmask_msi(xge_hal_channel_h channelh);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_mask_msix(xge_hal_device_h devh, int msi_id);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_unmask_msix(xge_hal_device_h devh, int msi_id);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xw#if defined(XGE_HAL_CONFIG_LRO)
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwvoid
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define __HAL_STATIC_DEVICE
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define __HAL_INLINE_DEVICE
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_rev(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_clear_rx(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_clear_tx(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_continue_irq(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_handle_irq(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_bar0(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_isrbar0(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_bar1(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl char *bar1);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_mask_tx(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_mask_rx(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_mask_all(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_unmask_tx(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_unmask_rx(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_device_unmask_all(xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined (XGE_HAL_CONFIG_LRO)
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_header_parse_token_u8(u8 *string,u16 offset);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_header_parse_token_u16(u8 *string,u16 offset);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_header_parse_token_u32(u8 *string,u16 offset);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_header_update_u8(u8 *string, u16 offset, u8 val);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_header_update_u16(u8 *string, u16 offset, u16 val);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_header_update_u32(u8 *string, u16 offset, u32 val);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp,
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_dtr_info_t *ext_info);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp,
7eced415e5dd557aef2d78483b5a7785f0e13670xw u32 *seglen, lro_t **p_lro,
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
7eced415e5dd557aef2d78483b5a7785f0e13670xw lro_t **lro_end3);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl lro_t **lro, xge_hal_dtr_info_t *ext_info,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_hal_device_t *hldev, lro_t **lro_end3);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_lro_next_session (xge_hal_device_t *hldev, int ring);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_lro_get_next_session(xge_hal_device_t *hldev);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro,
7eced415e5dd557aef2d78483b5a7785f0e13670xw int slot, u32 tcp_seg_len, int ts_off);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
7eced415e5dd557aef2d78483b5a7785f0e13670xw__hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#else /* XGE_FASTPATH_EXTERN */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define __HAL_STATIC_DEVICE static
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define __HAL_INLINE_DEVICE inline
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include "xgehal-device-fp.c"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* XGE_FASTPATH_INLINE */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl__EXTERN_END_DECLS
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* XGE_HAL_DEVICE_H */