Searched refs:MC_REV_MATCH (Results 1 - 5 of 5) sorted by relevance

/illumos-gate/usr/src/common/mc/mc-amd/
H A Dmcamd_rowcol_tbl.c811 if (MC_REV_MATCH(mcrev, bdp->revmask) && csmode < bdp->nmodes)
832 if (MC_REV_MATCH(mcrev, rcbm->mt_revmask) &&
853 if (MC_REV_MATCH(mcrev, swztp->swzt_revmask) &&
875 ((MC_REV_MATCH(mcrev, MC_F_REVS_BC) && csmode == 0x6) ||
876 (MC_REV_MATCH(mcrev, MC_F_REVS_DE) &&
H A Dmcamd_patounum.c532 if (!MC_REV_MATCH(rev, MC_F_REVS_FG))
560 if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
/illumos-gate/usr/src/uts/intel/sys/
H A Dmc_amd.h234 * as requirements arise. The MC_REV_* and MC_REV_MATCH etc macros
236 * individual bitfields of a register, perhaps using MC_REV_* and MC_REV_MATCH
268 #define MC_REV_MATCH(rev, revmask) X86_CHIPREV_MATCH(rev, revmask) macro
443 #define MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? \
477 #define MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 13 : 13)
478 #define MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 21 : 19)
480 #define MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 27 : 25)
481 #define MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 36 : 33)
483 #define MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 0 : 2)
485 #define MC_CSMASK(up, rev) (MC_REV_MATCH(re
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/illumos-gate/usr/src/uts/intel/io/mc-amd/
H A Dmcamd_drv.c215 return (MC_REV_MATCH(rev, MC_F_REVS_BCDE) ?
228 return (MC_REV_MATCH(rev, MC_F_REVS_BCDE) ?
565 if (MC_REV_MATCH(rev, MC_F_REVS_FG))
736 if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
811 if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
823 if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
827 } else if (MC_REV_MATCH(rev, MC_F_REV_E)) {
845 if (MC_REV_MATCH(rev, MC_F_REV_E)) {
848 } else if (MC_REV_MATCH(rev, MC_F_REVS_FG)) {
858 maskdivisor = MC_REV_MATCH(re
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H A Dmcamd_dimmcfg.c364 if (MC_REV_MATCH(rev, csmap_tbls[i].revmask) &&

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