Searched refs:MAX_CPU_NODES (Results 1 - 8 of 8) sorted by relevance

/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dmem_addr.h61 extern tad_t tad[MAX_CPU_NODES][MAX_TAD_DRAM_RULE];
62 extern sag_ch_t sag_ch[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
64 extern rir_t rir[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
66 extern dod_t dod_reg[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
H A Dintel_nhmdrv.c49 nvlist_t *inhm_mc_nvl[MAX_CPU_NODES];
52 char *inhm_mc_snapshot[MAX_CPU_NODES];
55 size_t inhm_mc_snapshotsz[MAX_CPU_NODES];
80 for (i = 0; i < MAX_CPU_NODES; i++) {
99 for (i = 0; i < MAX_CPU_NODES; i++) {
124 chip = getminor(dev) % MAX_CPU_NODES;
198 for (i = 0; i < MAX_CPU_NODES; i++) {
255 if (getminor(*devp) >= MAX_CPU_NODES) {
H A Dnhm_pci_cfg.c40 static ddi_acc_handle_t dev_pci_hdl[MAX_CPU_NODES][CPU_PCI_DEVS][CPU_PCI_FUNCS];
52 for (i = 0; i < MAX_CPU_NODES; i++) {
81 for (i = 0; i < MAX_CPU_NODES; i++) {
96 if (bus >= SOCKET_BUS(MAX_CPU_NODES) && bus <= SOCKET_BUS(0) &&
99 ASSERT(slot >= 0 && slot < MAX_CPU_NODES);
H A Ddimm_topo.c47 extern nvlist_t *inhm_mc_nvl[MAX_CPU_NODES];
50 extern char lockstep[MAX_CPU_NODES];
51 extern char mirror_mode[MAX_CPU_NODES];
52 extern char spare_channel[MAX_CPU_NODES];
H A Dintel_nhm.h44 #define MAX_CPU_NODES 2 macro
216 #define MAX_MEMORY_CONTROLLERS MAX_CPU_NODES
H A Dnhm_init.c328 for (slot = 0; slot < MAX_CPU_NODES; slot++) {
334 if (slot == MAX_CPU_NODES) {
H A Dmem_addr.c43 tad_t tad[MAX_CPU_NODES][MAX_TAD_DRAM_RULE];
44 sag_ch_t sag_ch[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
46 rir_t rir[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
48 dod_t dod_reg[MAX_CPU_NODES][CHANNELS_PER_MEMORY_CONTROLLER]
811 last = MAX_CPU_NODES;
/illumos-gate/usr/src/uts/i86pc/cpu/genuineintel/
H A Dgintel_main.c53 #define MAX_CPU_NODES 2 macro
55 uint32_t err_counter_array[MAX_CPU_NODES][ERR_COUNTER_INDEX][N_MC_COR_ECC_CNT];
56 uint8_t err_counter_index[MAX_CPU_NODES];
535 if (chipid < MAX_CPU_NODES) {

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