Searched refs:aCpus (Results 51 - 71 of 71) sorted by relevance

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/vbox/src/VBox/VMM/VMMR3/
H A DDBGFMem.cpp594 PVMCPU pVCpu = &pVM->aCpus[idCpu];
H A DPGMPool.cpp844 pVM->aCpus[idCpu].pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
855 CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
H A DSELM.cpp253 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
438 PVMCPU pVCpu = &pVM->aCpus[i];
461 PVMCPU pVCpu = &pVM->aCpus[0];
624 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
2597 PVMCPU pVCpu = &pVM->aCpus[0];
2665 PVMCPU pVCpu = &pVM->aCpus[0];
H A DPGMPhys.cpp1047 CPUMSetChangedFlags(&pVM->aCpus[i], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1199 CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
4015 pgmR3PoolClearAllRendezvous(pVM, &pVM->aCpus[0], NULL /* no need to flush the REM TLB as we already did that above */);
4056 PPGMCPU pPGM = &pVM->aCpus[idCpu].pgm.s;
4075 CPUMSetChangedFlags(&pVM->aCpus[idCpu], CPUM_CHANGED_GLOBAL_TLB_FLUSH);
H A DPGMDbg.cpp308 PVMCPU pVCpu = &pVM->aCpus[0];
364 PVMCPU pVCpu = &pVM->aCpus[0];
1741 pVCpu = &pVM->aCpus[0];
H A DCPUMDbg.cpp1388 int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegGstDescs, true /*fGuestRegs*/);
1390 rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegHyperDescs, false /*fGuestRegs*/);
H A DIOM.cpp252 PVMCPU pVCpu = &pVM->aCpus[iCpu];
320 PVMCPU pVCpu = &pVM->aCpus[iCpu];
H A DPATMPatch.cpp364 dest = pVM->pVMRC + RT_OFFSETOF(VM, aCpus[0].fLocalForcedActions);
451 int rc = PGMPhysSimpleReadGCPtr(&pVM->aCpus[0], pDest, pSrc, cb);
H A DCSAM.cpp356 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VPCU */
H A DPATM.cpp637 rc = PGMPhysSimpleReadGCPtr(&pDisInfo->pVM->aCpus[0], &pDis->abInstr[offInstr], uSrcAddr, cbMinRead);
/vbox/src/VBox/VMM/VMMR0/
H A DHMSVMR0.cpp472 PVMCPU pVCpu = &pVM->aCpus[i];
529 PVMCPU pVCpu = &pVM->aCpus[i];
537 PVMCPU pVCpu = &pVM->aCpus[i];
676 PVMCPU pVCpu = &pVM->aCpus[i];
677 PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
1077 int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
H A DCPUMR0.cpp319 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
H A DHMVMXR0.cpp888 PVMCPU pVCpu = &pVM->aCpus[i];
937 PVMCPU pVCpu = &pVM->aCpus[i];
949 (&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
978 PVMCPU pVCpu = &pVM->aCpus[i];
2775 PVMCPU pVCpu = &pVM->aCpus[i];
5274 rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
5339 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache);
5366 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache),
5367 ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache)));
/vbox/src/VBox/VMM/VMMAll/
H A DSELMAll.cpp873 PVMCPU pVCpu = &pVM->aCpus[0];
H A DCPUMAllRegs.cpp1636 PVMCPU pVCpu = &pVM->aCpus[i];
1797 PVMCPU pVCpu = &pVM->aCpus[i];
H A DTMAll.cpp254 PVMCPU pVCpuDst = &pVM->aCpus[pVM->tm.s.idTimerCpu];
773 PVMCPU pVCpuDst = &pVM->aCpus[pVM->tm.s.idTimerCpu];
H A DPGMAllHandler.cpp1616 PVMCPU pVCpu = &pVM->aCpus[i];
H A DPGMAll.cpp2764 PVMCPU pVCpu = &pVM->aCpus[0];
H A DPGMAllPool.cpp5333 pgmR3ExitShadowModeBeforePoolFlush(&pVM->aCpus[i]);
5449 PVMCPU pVCpu = &pVM->aCpus[i];
/vbox/src/VBox/VMM/testcase/
H A DtstVMStruct.h1381 GEN_CHECK_OFF(VM, aCpus);
/vbox/src/recompiler/
H A DVBoxRecompiler.c751 PVMCPU pVCpu = &pVM->aCpus[i];

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