Searched refs:instruction (Results 26 - 43 of 43) sorted by relevance

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/illumos-gate/usr/src/uts/sun4u/ml/
H A Dtrap_table.s59 * instead of "done" instruction to return back to the user mode. See
287 * handler will resume execution at the last instruction of the window
852 * The first instruction must be a membar for UltraSPARC-III
877 * illegal instruction trap
914 * trap instruction for V9 user trap handlers
1366 IMMU_EXCEPTION; /* 008 instruction access exception */
1367 NOT; /* 009 instruction access MMU miss */
1369 /* 00A instruction access error */
1371 ILLTRAP_INSTR; /* 010 illegal instruction */
1417 ITLB_MISS(tt0); /* 064 instruction acces
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/illumos-gate/usr/src/tools/ctf/dwarf/common/
H A Ddwarf_frame.c93 Start_instr_ptr points to the first byte of the frame instruction
100 offset. This makes it possible to expand an instruction stream
226 instruction. */
238 popped by a remember or restore instruction. Top_stack points to
245 pointer to the current frame instruction executed.
266 So if a frame instruction that computes an offset using an
314 if the augmentation is not right, only Frame instruction can be
986 If frame instruction decoding was right we would stop exactly at
2041 /* Expands a single frame instruction block
2053 Dwarf_Ptr instruction,
2052 dwarf_expand_frame_instructions(Dwarf_Cie cie, Dwarf_Ptr instruction, Dwarf_Unsigned i_length, Dwarf_Frame_Op ** returned_op_list, Dwarf_Signed * returned_op_count, Dwarf_Error * error) argument
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/illumos-gate/usr/src/common/bignum/amd64/
H A Dbignum_amd64_asm.s52 / the 64X64->128 bit unsigned multiply instruction.
222 / the 64X64->128 bit unsigned multiply instruction.
477 / used by the hardware MUL instruction. Use %r8, instead.
/illumos-gate/usr/src/uts/sparc/v9/ml/
H A Dsparcv9_subr.s450 * VAX movtuc instruction (sort of).
491 * VAX scanc instruction.
822 * Provide a C callable interface to the membar instruction.
1693 ! what the %o's contained prior to the save instruction.
/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dcheetah_copy.s287 * that might have different cache sizes, clock rates or instruction
334 * branch instruction on Cheetah, Jaguar, and Panther, the
343 * fall within the minimum number of 4 instruction fetch groups.
345 * instruction and the unrolled loops, then the alignment needs
1045 nop ! instruction alignment
1902 nop ! instruction alignment
2098 nop ! instruction alignment
2153 nop ! instruction alignment
2697 nop ! instruction alignment
2890 nop ! instruction alignmen
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H A Dopl_olympus_copy.s282 * that might have different cache sizes, clock rates or instruction
334 * fall within the minimum number of 4 instruction fetch groups.
336 * instruction and the unrolled loops, then the alignment needs
996 nop ! instruction alignment
1834 nop ! instruction alignment
2030 nop ! instruction alignment
2085 nop ! instruction alignment
2620 nop ! instruction alignment
2813 nop ! instruction alignment
2868 nop ! instruction alignmen
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H A Dspitfire_copy.s1734 .empty ! allow next instruction in delay slot
2271 ! pointer. A very fast 4 instruction loop.
3523 ! pointer. A very fast 4 instruction loop.
H A Dopl_olympus_asm.s554 * the stores from all processors so that a FLUSH instruction is only needed
556 * the end of a sequence of stores that updates the instruction stream to
1689 * instruction after the flushw does not cause a fill trap. The sun4u
1691 * except at the restore instruction at user_rtt. On OPL systems the
1923 flush %i0 ! flush instruction pipeline
2082 * line in the instruction cache.
2130 * Halt the current strand with the suspend instruction.
2132 * instruction mnemonic, use byte code for now.
2141 * Pause the current strand with the sleep instruction.
2143 * instruction mnemoni
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/illumos-gate/usr/src/uts/sun4v/cpu/
H A Dgeneric_copy.s255 .empty ! allow next instruction in delay slot
669 ! pointer. A very fast 4 instruction loop.
948 ! pointer. A very fast 4 instruction loop.
H A Dniagara_copy.s2565 .empty ! allow next instruction in delay slot
4462 ! pointer. A very fast 4 instruction loop.
6654 ! pointer. A very fast 4 instruction loop.
/illumos-gate/usr/src/common/crypto/aes/amd64/
H A Daes_intel.s81 * of "Add support to Intel AES-NI instruction set for x86_64 platform".
646 / with the "AES Inverse Mix Columns" instruction
/illumos-gate/usr/src/uts/i86pc/ml/
H A Dcpr_wakecode.s404 * The instruction after enabling paging in CR0 MUST be a branch.
695 / restore %fsbase %gsbase %kgbase registers using wrmsr instruction
/illumos-gate/usr/src/uts/sun4u/tazmo/io/
H A Denvctrl.c3637 eHc_write_tda8444(struct eHc_envcunit *ehcp, int byteaddress, int instruction, argument
3645 ASSERT(instruction == 0xf || instruction == 0x0);
3648 control = (instruction << 4) | subaddress;
/illumos-gate/usr/src/lib/libc/capabilities/sun4u/common/
H A Dmemcpy.s327 call .+8 ! get the address of this instruction in %o7
330 jmp %o7 + 16 ! jump to the starting ldd instruction
/illumos-gate/usr/src/uts/intel/ia32/ml/
H A Dlock_prim.s1109 * instruction.
1136 * The workaround is to place a fencing instruction (lfence) between the
1137 * mutex operation and the subsequent read-modify-write instruction.
1139 * This routine hot patches the lfence instruction on top of the space
1151 * 6323525 patch points (points past the lfence instruction to the
1223 .byte 0xf, 0xae, 0xe8 / [lfence instruction]
/illumos-gate/usr/src/boot/sys/boot/i386/btx/btx/
H A Dbtx.S44 .set PSL_D,0x00000400 # String instruction direction
/illumos-gate/usr/src/lib/libc/capabilities/sun4u-opl/common/
H A Dmemcpy.s330 ! adjust instruction alignment
/illumos-gate/usr/src/lib/libc/capabilities/sun4u-us3/common/
H A Dmemcpy.s353 ! adjust instruction alignment

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