Searched refs:CPU (Results 276 - 299 of 299) sorted by relevance

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/illumos-gate/usr/src/uts/common/disp/
H A Dts.c1332 * so we need to calculate how much CPU time it used
1335 * CPU caps are not enforced on exiting processes - it is
1395 * This thread may be placed on wait queue by CPU Caps. In this case we
1397 * Do not enforce CPU caps on threads running at a kernel priority
1526 * Account for time spent on CPU before going to sleep.
1715 * Keep track of thread's project CPU usage. Note that projects
1798 cpu_t *cp = CPU;
2043 * Collect CPU usage spent before yielding
2398 * its CPU timeleft from the quantum
H A Dfss.c59 * (zones and projects) each get their configured share of CPU. This is in
65 * collection will only get CPU resources when there are no other processes
66 * that need CPU. The cpu-share is used as one of the inputs to calculate a
71 * The FSS class should approximate TS behavior when there are excess CPU
76 * Projects in a zone compete with each other for CPU time, receiving CPU
112 * The usage value is the recent CPU usage for all of the threads in the
1324 * per-thread CPU usages.
2123 * calculate how much CPU time it used since it was charged last time.
2125 * CPU cap
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/illumos-gate/usr/src/uts/common/sys/crypto/
H A Dimpl.h80 #define CPU_SEQID (CPU->cpu_seqid)
88 * Per-CPU structure used by a provider to keep track of
181 * pd_percpu_bins: Pointer to an array of per-CPU structures
/illumos-gate/usr/src/uts/sun4u/sunfire/io/
H A Djtag.c124 #define CPU_TYPE_LEN 12 /* CPU board ring length */
1280 * CPU frequency may be incorrectly displayed. Coupled with the lack of
1282 * CPU board is physically plugged in, the default is not to get any
1283 * CPU information.
1975 cs_value = ldphysio(AC_BCSR(FHC_CPU2BOARD(CPU->cpu_id)));
/illumos-gate/usr/src/uts/common/dtrace/
H A Dfasttrap.c870 cpu_t *cur, *cpu = CPU;
/illumos-gate/usr/src/uts/sfmmu/vm/
H A Dhat_sfmmu.h543 * Per-MMU context domain structure. This is instantiated the first time a CPU
554 * The max number of context IDs supported on every CPU in this
567 * structure. When the last CPU in an MMU context domain is unconfigured,
570 * The CPU set of configured CPUs for this MMU context domain. Used
611 * a CPU from the platform.
2017 * Macro to get hat per-MMU cnum on this CPU.
2023 CPU_ADDR(scr, cnum); /* scr = load CPU struct addr */ \
2046 * Macro to get this CPU's tsbmiss area.
2053 add tsbmiss, tmp1, tsbmiss /* tsbmiss area of CPU */
2315 * MMU-specific functions optionally imported from the CPU modul
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/illumos-gate/usr/src/uts/common/io/
H A Dstream.c4274 if (CPU->cpu_seqid != hp->cpu_seqid) {
4275 hp->cpu_seqid = CPU->cpu_seqid;
/illumos-gate/usr/src/uts/common/fs/doorfs/
H A Ddoor_sys.c1446 cpu_t *cp = CPU;
1874 cp = CPU;
/illumos-gate/usr/src/uts/common/vm/
H A Dvm_as.c886 CPU_STATS_ADDQ(CPU, vm, as_fault, 1);
888 CPU_STATS_ADDQ(CPU, vm, kernel_asflt, 1);
/illumos-gate/usr/src/uts/sun4u/starfire/sys/
H A Didn.h963 * cpuid Local domain's CPU->cpu_id that sending message.
1015 (((uint64_t)CPU->cpu_id & UINT64_C(_IDNPD_CPUID_MASK)) << \
/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dspitfire_asm.s488 SFMMU_CPU_CNUM(%o1, %g1, %g2) /* %g1 = sfmmu cnum on this CPU */
561 SFMMU_CPU_CNUM(%g2, %g3, %g4) /* %g3 = sfmmu cnum on this CPU */
600 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
1113 ! into the CPU module's C error handler. Note that we also branch
1897 * from the clock CPU. It atomically increments the outstanding request
/illumos-gate/usr/src/uts/sun4u/ngdr/io/
H A Ddr_mem.c376 (cpuid == CPU_CURRENT) ? CPU->cpu_id : cpuid);
/illumos-gate/usr/src/lib/fm/topo/libtopo/common/
H A Dhc.c152 { CPU, TOPO_STABILITY_PRIVATE },
/illumos-gate/usr/src/uts/intel/io/scsi/adapters/pvscsi/
H A Dpvscsi.c1057 rdesc->vcpuHint = CPU->cpu_id;
/illumos-gate/usr/src/uts/common/io/nvme/
H A Dnvme.c34 * or MSI if supported. The driver wants to have one interrupt vector per CPU,
95 * an I/O queue. The queue is selected by taking the CPU id modulo the number of
2980 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1;
/illumos-gate/usr/src/uts/common/io/myri10ge/drv/
H A Dmyri10ge.c414 * iterate over all per-CPU caches, and add contents into
418 /* take per-CPU free list */
523 /* prepend buffer locklessly to per-CPU freelist */
524 putp = (void *)&jpool->cpu[CPU->cpu_seqid & MYRI10GE_MAX_CPU_MASK].head;
1716 * for the connection to try to keep connections CPU local
1785 slice = CPU->cpu_id & (mgp->num_slices - 1);
/illumos-gate/usr/src/common/bignum/
H A Dbignumimpl.c186 * Cache the result, as the CPU can't change.
198 cached_result = (cpuid_getvendor(CPU) == X86_VENDOR_Intel);
/illumos-gate/usr/src/uts/common/io/mac/
H A Dmac_datapath_setup.c130 * rings is based on specified bandwidth, CPU speed and number of CPUs in
139 * list is used to walk the list of all MAC threads when a CPU is
525 /* CPU RECONFIGURATION AND FANOUT COMPUTATION ROUTINES */
528 * Return the next CPU to be used to bind a MAC kernel thread.
595 * dependent upon CPU speed, the number of Rx rings configured, and
643 * Soft ring computation using CPU speed and specified
647 cpu_speed = (uint64_t)CPU->cpu_type_info.pi_clock;
656 * of bandwidth and CPU speed. To keep this simple,
657 * let's use this rule: 1GHz CPU can handle 1Gbps.
659 * for soft rings. Assumption is that CPU speed
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H A Dmac_client.c3392 * 'CPU' must be accessed just once and used to compute the index into the
3395 * another cpu any time and so we can't use 'CPU' more than once for the
3401 (mytx) = &(mcip)->mci_tx_pcpu[CPU->cpu_seqid & mac_tx_percpu_cnt]; \
/illumos-gate/usr/src/uts/intel/ia32/ml/
H A Di86_subr.s1385 / triple-fault the CPU.
/illumos-gate/usr/src/uts/common/inet/tcp/
H A Dtcp_input.c86 * is per CPU. So the total number of connections in a stack is the sum of all
112 (uint64_t *)&(tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_conn_cnt); \
1831 * CPU for obvious locality reason so this leaves the listener to
1833 * is binding, the CPU that will get interrupted by the NIC whose
1836 * CPU is interrupted by virtue of incoming connection's squeue.
/illumos-gate/usr/src/uts/common/os/
H A Dkmem.c134 * (bypassing the per-CPU magazine layer). The response tells kmem which of the
999 size_t kmem_failure_log_size; /* failure log [4 pages per CPU] */
1000 size_t kmem_slab_log_size; /* slab create log [4 pages per CPU] */
1472 kmem_cpu_log_header_t *clhp = &lhp->lh_cpu[CPU->cpu_seqid];
2248 * there are no locks because only one CPU calls kmem during a crash
2346 * for the calling CPU.
2535 * If there's an object available in the current CPU's
2686 * Used when there's no room to free a buffer to the per-CPU cache.
2688 * caller should try freeing to the per-CPU cache again.
2789 * If there's a slot available in the current CPU'
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H A Dstrsubr.c3918 * the esb queue does not match the new CPU, that is OK.
3923 int qindex = CPU->cpu_seqid >> esbq_log2_cpus_per_q;
5375 * selected by current cpu_seqid and current CPU can change at any moment. XXX
H A Dsunddi.c5135 * timeout which is either running on another CPU, or has already
8673 ASSERT(CPU_ON_INTR(CPU) == 0); /* cannot be high level */

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