Searched refs:CPU (Results 176 - 200 of 299) sorted by relevance

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/illumos-gate/usr/src/uts/intel/pcbe/
H A Dcore_pcbe.c1135 if (cpuid_getvendor(CPU) != X86_VENDOR_Intel)
1266 if ((cpuid_getfamily(CPU) == 6) &&
1267 ((cpuid_getmodel(CPU) == 15) || (cpuid_getmodel(CPU) == 23) ||
1268 (cpuid_getmodel(CPU) == 29))) {
1277 versionid, cpuid_getfamily(CPU), cpuid_getmodel(CPU));
1320 model = cpuid_getmodel(CPU);
H A Dp4_pcbe.c122 #define P4_THIS_USR 0x1 /* HTT: Measure usr events on this logical CPU */
123 #define P4_THIS_SYS 0x2 /* HTT: Measure os events on this logical CPU */
124 #define P4_SIBLING_USR 0x4 /* HTT: Measure os events on other logical CPU */
125 #define P4_SIBLING_SYS 0x8 /* HTT: Measure usr events on other logical CPU */
126 #define P4_PMI 0x10 /* HTT: Set PMI bit for local logical CPU */
452 if (cpuid_getvendor(CPU) != X86_VENDOR_Intel ||
453 cpuid_getfamily(CPU) != P4_FAMILY)
846 * logical CPU this configuration will eventually be programmed
897 * we know which logical CPU we'll be programming.
935 int lid = cpuid_get_clogid(CPU); /* Logica
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/illumos-gate/usr/src/uts/intel/ia32/os/
H A Dsysi86.c349 *((system_desc_t *)&CPU->cpu_gdt[GDT_LDT]) = curproc->p_ldt_desc;
364 *((system_desc_t *)&CPU->cpu_gdt[GDT_LDT]) = null_sdesc;
H A Darchdep.c859 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
860 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
1329 * CPU was overwritten. panic_cpu has the correct values.
1333 cpu = (panicstr && CPU->cpu_id == panic_cpu.cpu_id)? &panic_cpu : CPU;
/illumos-gate/usr/src/uts/common/inet/
H A Dtcp_impl.h422 (uint64_t *)&(tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_conn_cnt)
426 (uint64_t *)&(tcps)->tcps_sc[CPU->cpu_seqid]->tcp_sc_conn_cnt)
/illumos-gate/usr/src/uts/common/os/
H A Ddumpsubr.c92 * parallel lzjb versus parallel bzip2. Therefore, the CPU count
365 * parallel at dump time; each CPU creates a single stream of
404 ulong_t *helpermap; /* set of dumpsys helper CPU ids */
531 * For parallel dumps, the number of helpers is ncpu-1. The CPU
533 * panic CPU does lzjb compression (it is tagged as MAINHELPER.)
590 * One CPU runs dumpsys, the rest are helpers.
1819 CPU->cpu_id, (uint32_t)(pa >> 32), (uint32_t)pa);
2174 * panic dump the helper CPUs communicate with the panic CPU using
2176 * panic CPU.
2194 hp->helper = CPU
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H A Dprintf.c87 on_intr = CPU_ON_INTR(CPU) ||
H A Dcallout.c49 static callout_table_t *callout_boot_ct; /* Boot CPU's callout tables */
974 * directly or indirectly acquire cpu_lock. CPU offline waits for pending
977 * during CPU offline.
1000 * We disable kernel preemption so that we remain on the same CPU
1002 * we can avoid X-calls if we are on the same CPU.
1006 * to go to sleep and later migrate to another CPU. This should be
1011 ct = &callout_table[CALLOUT_TABLE(type, CPU->cpu_seqid)];
1314 * order to avoid lots of X-calls to the CPU associated
1905 * function is called during CPU online. cpu_lock is held at this
1961 * Locate the cache corresponding to the onlined CPU'
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/illumos-gate/usr/src/uts/sun4u/starfire/os/
H A Dbbus_intr.c142 processorid_t cpu_id = CPU->cpu_id;
/illumos-gate/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu_asm.s102 * currently running on this CPU.
111 ! current CPU tsbmiss->usfmmup == victim sfmmup) {
579 ldub [%o0 + SFMMU_TTEFLAGS], %o3 ! per-CPU tsbmiss area.
/illumos-gate/usr/src/uts/sun4v/promif/
H A Dpromif_emul.c351 CPUSET_DEL(other_cpus, CPU->cpu_id);
411 "CPU instance %d has no 'id' property", i);
470 * Take over rtba for the boot CPU. The rtba for
/illumos-gate/usr/src/uts/sun4/os/
H A Dprom_subr.c197 * caller's CPU to continue to perform useful work in the interim. Service
198 * routines may also be called early in boot as part of slave CPU startup
204 * lock to be acquired recursively by the owning CPU after disabling preemption.
209 * If the current CPU is an "adult" (determined by testing cpu_m.mutex_ready),
212 * we drop the lock and prom_holdcnt returns to zero. If the current CPU is
213 * an adult and the lock is held by another adult CPU, we can safely sleep
216 * from above LOCK_LEVEL on any adult CPU. Finally, if recursive entry is
217 * attempted on an adult CPU, we must also verify that curthread matches the
219 * threads do not step on other threads running on the same CPU.
231 * If a CPU i
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/illumos-gate/usr/src/uts/i86pc/os/
H A Dmp_implfuncs.c201 return (CPU->cpu_id);
H A Dmicrocode.c59 * mcpu_ucode_info for the boot CPU. Statically allocated.
176 * Allocate/free a buffer used to hold ucode data. Space for the boot CPU is
238 * or when the cached microcode doesn't match the CPU being processed.
280 * Find the equivalent CPU id in the equivalence table.
317 * Not done on boot CPU.
344 /* Get the equivalent CPU id. */
353 /* No equivalent CPU id found, assume outdated microcode file. */
363 * by setting their CPU revision to an invalid value.
400 * this CPU, if exists.
417 /* get equivalent CPU i
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H A Dmachdep.c401 ulong_t s = clear_int_flag(); /* fast way to keep CPU from changing */
404 CPUSET_ALL_BUT(xcset, CPU->cpu_id);
680 * set_idle_cpu is called from idle() when a CPU becomes idle.
694 * unset_idle_cpu is called from idle() when a CPU is no longer idle.
894 * If we're not the panic CPU, we wait in panic_idle for reboot.
1083 * Because the microstate is only updated when the CPU's state
1105 * cpu_intracct[] is used to identify time spent in each CPU
1124 * of (now - cpu_mstate_start) by a change in CPU mstate that
1298 * by looking up the %cs selector process's LDT or the CPU's GDT.
1332 descrp = &CPU
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/illumos-gate/usr/src/uts/common/sys/
H A Dkmem_impl.h50 * 2. cc_lock in order by CPU ID
183 * The "CPU" macro loads a cpu_t that refers to the cpu that the current
195 * So, there is no need to disable kernel preemption while using the CPU macro
201 ((kmem_cpu_cache_t *)((char *)(&cp->cache_cpu) + CPU->cpu_cache_offset))
275 int cc_flags; /* CPU-local copy of cache_flags */
406 * Per-CPU layer
H A Dlgrp.h93 * dynamically so they are hashed to CPU buckets to reduce cache
117 (&LGRP_STAT(stats, (CPU->cpu_id) & LGRP_CPU_BUCKET_MASK, \
166 LGRP_LOADAVG_SCALE, /* load unit of one CPU bound thread */
302 * 2) Setup root lgroup and add CPU 0 to lgroup(s) (called near beginning of
305 * 3) Probe from CPU 0 and copy and release any BOP_ALLOC-ed memory temporarily
333 LGRP_MEM_POLICY_NEXT_CPU, /* Near next CPU to touch memory */
481 * Macro for testing if a CPU is contained in an lgrp.
516 * Return true if lgrp has CPU resources in the cpupart
526 extern int lgrp_initialized; /* single-CPU initialization done */
H A Ddtrace.h1006 #define DTRACEOPT_CPU 8 /* CPU to trace */
1046 * structure. This describes which CPU user-level is interested in, and
1060 uint32_t dtbd_cpu; /* CPU or DTRACE_CPUALL */
1203 #define DTRACE_CLASS_CPU 1 /* CPU-module-specific */
2325 (cpu_core[CPU->cpu_id].cpuc_dtrace_flags & (flag))
2328 (cpu_core[CPU->cpu_id].cpuc_dtrace_flags |= (flag))
2331 (cpu_core[CPU->cpu_id].cpuc_dtrace_flags &= ~(flag))
/illumos-gate/usr/src/uts/common/vm/
H A Danon.h211 * Since each CPU has its own bucket in ani_free_pool, there should be no
217 index = (CPU->cpu_seqid & (ANI_MAX_POOL - 1)); \
/illumos-gate/usr/src/uts/i86xpv/io/psm/
H A Dxpv_psm.c277 * any missed operations (e.g. bind to CPU)
303 * generates an interprocessor interrupt to another CPU
367 } while (cpuid != CPU->cpu_id);
529 cpu_t *cpu = CPU;
595 struct cpu *cpu = CPU;
1606 /* CPU is not up or interrupt is disabled. Fall back to 0 */
/illumos-gate/usr/src/uts/i86xpv/os/
H A Dxen_machdep.c527 if (CPU->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask == 0) {
529 "CPU->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask not set\n");
666 prom_printf("CPU%d pending %d mask %d sel %lx\n",
825 SUSPEND_DEBUG("%d: xen_shutdown_handler: \"%s\"\n", CPU->cpu_id, str);
854 SUSPEND_DEBUG("%d: trying again\n", CPU->cpu_id);
955 "xen_get_mc_physinfo failure: can't allocate CPU array");
961 "physical CPU info");
/illumos-gate/usr/src/uts/sparc/fpu/
H A Dfpu_simulator.c619 * fp_emulator simulates FPU and CPU-FPU instructions; reads and writes FPU
762 cmn_err(CE_WARN, "CPU%d: kstat_create for fpu_traps failed",
763 CPU->cpu_id);
772 cmn_err(CE_WARN, "CPU%d: kstat_create for fpu_info failed",
773 CPU->cpu_id);
781 cmn_err(CE_WARN, "CPU%d: kstat_create for vis_info failed",
782 CPU->cpu_id);
/illumos-gate/usr/src/uts/i86pc/io/apix/
H A Dapix.c169 apic_cpu_ops, /* CPU control interface. */
212 * will be bound to the same CPU.
219 * Maximum number of vectors in a CPU that can be used for interrupt
331 int cpuid = CPU->cpu_id;
368 if (cpuid_have_cr8access(CPU))
394 * Number of available per-CPU vectors excluding
647 struct cpu *cpu = CPU;
648 uint32_t cpuid = CPU->cpu_id;
918 * Bind interrupts to specified CPU
1003 /* We know this CPU
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/illumos-gate/usr/src/uts/sun4u/starcat/io/
H A Ddrmach.c332 * There is a known HW bug where a Jaguar CPU in Safari port 0 (SBX/P0)
779 * Check if a CPU node is part of a CMP.
1063 * On Starcat, there is no CPU driver, so it is
1064 * not necessary to configure any CPU nodes.
2850 if (STARCAT_CPUID_TO_PORTID(CPU->cpu_id) == mp->dev.portid) {
2968 if (mp->dev.portid == STARCAT_CPUID_TO_PORTID(CPU->cpu_id)) {
3080 DRMACH_PR("preparing MC MADR rename script (master is CPU%d):\n",
3081 CPU->cpu_id);
3092 if (mp->dev.portid == STARCAT_CPUID_TO_PORTID(CPU->cpu_id)) {
3103 if (mp->dev.portid == STARCAT_CPUID_TO_PORTID(CPU
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/illumos-gate/usr/src/uts/common/inet/nca/
H A Dnca.h200 #define SQT_BIND_ANY 0x01000000 /* bind worker thread to any CPU */
201 #define SQT_BIND_TO 0x02000000 /* bind worker thread to speced CPU */
703 _p->cpu = CPU->cpu_seqid; \
845 * Per CPU instance structure.
857 uint32_t dcb_readers; /* count of dcb_list readers for this CPU */
875 extern nca_cpu_t *nca_gv; /* global per CPU state indexed by cpu_seqid */
934 cpu = CPU->cpu_seqid; \
941 /* May be the last reader for this CPU */ \
965 /* May be the last reader for this CPU */ \
1060 * All if_t are associated with a CPU an
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