03831d35f7499c87d51205817c93e9a8d42c4baestevel * CDDL HEADER START
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The contents of this file are subject to the terms of the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Common Development and Distribution License (the "License").
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You may not use this file except in compliance with the License.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
03831d35f7499c87d51205817c93e9a8d42c4baestevel * See the License for the specific language governing permissions
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and limitations under the License.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * When distributing Covered Code, include this CDDL HEADER in each
03831d35f7499c87d51205817c93e9a8d42c4baestevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If applicable, add the following below this CDDL HEADER, with the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * fields enclosed by brackets "[]" replaced with your own identifying
03831d35f7499c87d51205817c93e9a8d42c4baestevel * information: Portions Copyright [yyyy] [name of copyright owner]
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CDDL HEADER END
56f33205c9ed776c3c909e07d52e94610a675740Jonathan Adams * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Use is subject to license terms.
03831d35f7499c87d51205817c93e9a8d42c4baestevel#include <sys/hotplug/hpctrl.h> /* XXX should be included by schpc.h */
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* defined in ../ml/drmach.il.cpp */
03831d35f7499c87d51205817c93e9a8d42c4baestevelextern void flush_ecache_il(int64_t physaddr, int size, int linesz);
03831d35f7499c87d51205817c93e9a8d42c4baestevelextern void flush_dcache_il(void);
03831d35f7499c87d51205817c93e9a8d42c4baestevelextern void flush_icache_il(void);
03831d35f7499c87d51205817c93e9a8d42c4baestevelextern void flush_pcache_il(void);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* defined in ../ml/drmach_asm.s */
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* XXX here until provided by sys/dman.h */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_EXPSLOT2BNUM(exp, slot) (((exp) << 1) + (slot))
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_SLICE_TO_PA(s) (((s) & DRMACH_SLICE_MASK) << 37)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_PA_TO_SLICE(a) (((a) >> 37) & DRMACH_SLICE_MASK)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * DRMACH_MEM_SLICE_SIZE and DRMACH_MEM_USABLE_SLICE_SIZE define the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * available address space and the usable address space for every slice.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * There must be a distinction between the available and usable do to a
03831d35f7499c87d51205817c93e9a8d42c4baestevel * restriction imposed by CDC memory size.
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_MEM_SLICE_SIZE (1ull << 37) /* 128GB */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_MEM_USABLE_SLICE_SIZE (1ull << 36) /* 64GB */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_MC_ADDR(mp, bank) ((mp)->madr_pa + 16 + 8 * (bank))
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_MC_ASI_ADDR(mp, bank) (DRMACH_MC_ADDR(mp, bank) & 0xFF)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The Cheetah's Safari Configuration Register and the Schizo's
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Safari Control/Status Register place the LPA base and bound fields in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * same bit locations with in their register word. This source code takes
03831d35f7499c87d51205817c93e9a8d42c4baestevel * advantage of this by defining only one set of LPA encoding/decoding macros
03831d35f7499c87d51205817c93e9a8d42c4baestevel * which are shared by various Cheetah and Schizo drmach routines.
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_LPA_BASE_TO_PA(scr) (((scr) & DRMACH_LPA_BASE_MASK) << 34)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_LPA_BND_TO_PA(scr) (((scr) & DRMACH_LPA_BND_MASK) << 28)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_PA_TO_LPA_BASE(pa) (((pa) >> 34) & DRMACH_LPA_BASE_MASK)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_PA_TO_LPA_BND(pa) (((pa) >> 28) & DRMACH_LPA_BND_MASK)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Name properties for frequently accessed device nodes.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Maximum value of processor Safari Timeout Log (TOL) field of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Safari Config reg (7 secs).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_board_t flag definitions
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel int (*n_getproplen)(struct drmach_node *node, char *name,
03831d35f7499c87d51205817c93e9a8d42c4baestevel int (*n_getprop)(struct drmach_node *node, char *name,
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel sbd_error_t *(*status)(drmachid_t, drmach_status_t *);
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel uint64_t scsr_pa; /* PA of Schizo Control/Status Register */
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel sbd_error_t *(*found)(void *a, const char *, int, drmachid_t);
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef enum {
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The following global is read as a boolean value, non-zero is true.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If zero, DR copy-rename and cpu poweron will not set the processor
03831d35f7499c87d51205817c93e9a8d42c4baestevel * LPA settings (CBASE, CBND of Safari config register) to correspond
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to the current memory slice map. LPAs of processors present at boot
03831d35f7499c87d51205817c93e9a8d42c4baestevel * will remain as programmed by POST. LPAs of processors on boards added
03831d35f7499c87d51205817c93e9a8d42c4baestevel * by DR will remain NULL, as programmed by POST. This can be used to
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to override the per-board L1SSFLG_THIS_L1_NULL_PROC_LPA flag set by
03831d35f7499c87d51205817c93e9a8d42c4baestevel * POST in the LDCD (and copied to the GDCD by SMS).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_reprogram_lpa and L1SSFLG_THIS_L1_NULL_PROC_LPA do not apply
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to Schizo device LPAs. These are always set by DR.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * There is a known HW bug where a Jaguar CPU in Safari port 0 (SBX/P0)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * can fail to receive an XIR. To workaround this issue until a hardware
03831d35f7499c87d51205817c93e9a8d42c4baestevel * fix is implemented, we will exclude the selection of these CPUs.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Setting this to 0 will allow their selection again.
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_iocage_exclude_jaguar_port_zero = 1;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Setting to non-zero will enable delay before all disconnect ops.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Default delay is slightly greater than the max processor Safari timeout.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This delay is intended to ensure the outstanding Safari activity has
03831d35f7499c87d51205817c93e9a8d42c4baestevel * retired on this board prior to a board disconnect.
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic clock_t drmach_unclaim_usec_delay = DRMACH_SAF_TOL_MAX + 10;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * By default, DR of non-Panther procs is not allowed into a Panther
03831d35f7499c87d51205817c93e9a8d42c4baestevel * domain with large page sizes enabled. Setting this to 0 will remove
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the restriction.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Used to pass updated LPA values to procs.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Protocol is to clear the array before use.
8682d1ef2a0960ed5a9f05b9448eaa3e68ac931fRichard Lowestatic void drmach_fini(void);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_device_new(drmach_node_t *,
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_cpu_new(drmach_device_t *, drmachid_t *);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_mem_new(drmach_device_t *, drmachid_t *);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_pci_new(drmach_device_t *, drmachid_t *);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_io_new(drmach_device_t *, drmachid_t *);
8682d1ef2a0960ed5a9f05b9448eaa3e68ac931fRichard Lowestatic sbd_error_t *drmach_board_release(drmachid_t);
8682d1ef2a0960ed5a9f05b9448eaa3e68ac931fRichard Lowestatic sbd_error_t *drmach_board_status(drmachid_t, drmach_status_t *);
8682d1ef2a0960ed5a9f05b9448eaa3e68ac931fRichard Lowestatic sbd_error_t *drmach_cpu_release(drmachid_t);
8682d1ef2a0960ed5a9f05b9448eaa3e68ac931fRichard Lowestatic sbd_error_t *drmach_cpu_status(drmachid_t, drmach_status_t *);
8682d1ef2a0960ed5a9f05b9448eaa3e68ac931fRichard Lowestatic sbd_error_t *drmach_mem_release(drmachid_t);
8682d1ef2a0960ed5a9f05b9448eaa3e68ac931fRichard Lowestatic sbd_error_t *drmach_mem_status(drmachid_t, drmach_status_t *);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic dev_info_t *drmach_node_ddi_get_dip(drmach_node_t *np);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_node_ddi_get_prop(drmach_node_t *np,
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_node_ddi_get_proplen(drmach_node_t *np,
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic dev_info_t *drmach_node_obp_get_dip(drmach_node_t *np);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_node_obp_get_prop(drmach_node_t *np,
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_node_obp_get_proplen(drmach_node_t *np,
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_mbox_trans(uint8_t msgtype, int bnum,
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_iocage_setup(dr_testboard_req_t *,
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_iocage_cpu_return(drmach_device_t *dp,
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_iocage_mem_return(dr_testboard_reply_t *tbr);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_i_status(drmachid_t id, drmach_status_t *stat);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic void drmach_cpu_read(uint64_t arg1, uint64_t arg2);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_cpu_read_scr(drmach_cpu_t *cp, uint64_t *scr);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic void drmach_bus_sync_list_update(void);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic void drmach_slice_table_update(drmach_board_t *, int);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_portid2bnum(int);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic void drmach_msg_memslice_init(dr_memslice_t slice_arr[]);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic void drmach_msg_memregs_init(dr_memregs_t regs_arr[]);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_panther_boards(void);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int drmach_name2type_idx(char *);
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_MEMLIST_DUMP if (drmach_debug) MEMLIST_DUMP
03831d35f7499c87d51205817c93e9a8d42c4baestevelint drmach_debug = 0; /* set to non-zero to enable debug messages */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_PR _NOTE(CONSTANTCONDITION) if (0) printf
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_MEMLIST_DUMP _NOTE(CONSTANTCONDITION) if (0) MEMLIST_DUMP
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif /* DEBUG */
03831d35f7499c87d51205817c93e9a8d42c4baestevel ((id != 0) && \
03831d35f7499c87d51205817c93e9a8d42c4baestevel ((id != 0) && \
03831d35f7499c87d51205817c93e9a8d42c4baestevel ((id != 0) && \
03831d35f7499c87d51205817c93e9a8d42c4baestevel ((id != 0) && \
03831d35f7499c87d51205817c93e9a8d42c4baestevel ((id != 0) && \
03831d35f7499c87d51205817c93e9a8d42c4baestevel ((id != 0) && \
03831d35f7499c87d51205817c93e9a8d42c4baestevel (DRMACH_OBJ(id)->isa == (void *)drmach_board_new || \
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel sbd_error_t *(*new)(drmach_device_t *, drmachid_t *);
03831d35f7499c87d51205817c93e9a8d42c4baestevel {"SUNW,UltraSPARC-III", DRMACH_DEVTYPE_CPU, drmach_cpu_new },
03831d35f7499c87d51205817c93e9a8d42c4baestevel {"SUNW,UltraSPARC-III+", DRMACH_DEVTYPE_CPU, drmach_cpu_new },
03831d35f7499c87d51205817c93e9a8d42c4baestevel {"memory-controller", DRMACH_DEVTYPE_MEM, drmach_mem_new },
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach autoconfiguration data structures and interfaces
f500b19684bd0346ac05bec02a50af07f369da1aRichard Bean "Sun Fire 15000 DR"
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_boards_rwlock is used to synchronize read/write
03831d35f7499c87d51205817c93e9a8d42c4baestevel * access to drmach_boards array between status and board lookup
03831d35f7499c87d51205817c93e9a8d42c4baestevel * as READERS, and assign, and unassign threads as WRITERS.
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_i_lock, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel rw_init(&drmach_boards_rwlock, NULL, RW_DEFAULT, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_xt_mb = (uchar_t *)vmem_alloc(static_alloc_arena,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_node_* routines serve the purpose of separating the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * rest of the code from the device tree and OBP. This is necessary
03831d35f7499c87d51205817c93e9a8d42c4baestevel * because of In-Kernel-Probing. Devices probed after stod, are probed
03831d35f7499c87d51205817c93e9a8d42c4baestevel * by the in-kernel-prober, not OBP. These devices, therefore, do not
03831d35f7499c87d51205817c93e9a8d42c4baestevel * have dnode ids.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_node_obp_get_parent(drmach_node_t *np, drmach_node_t *pp)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel pp->here = (void *)(uintptr_t)prom_parentnode(nodeid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * dip doesn't have to be held here as we are called
03831d35f7499c87d51205817c93e9a8d42c4baestevel * from ddi_walk_devs() which holds the dip.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Set "here" to NULL so that unheld dip is not accessible
03831d35f7499c87d51205817c93e9a8d42c4baestevel * outside ddi_walk_devs()
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* initialized args structure for callback */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Root node doesn't have to be held in any way.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni ddi_walk_devs(ddi_root_node(), drmach_node_ddi_walk_cb, (void *)&nargs);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* initialized args structure for callback */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* save our new position within the tree */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* save our new position within the tree */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_node_ddi_get_parent(drmach_node_t *np, drmach_node_t *pp)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check if a CPU node is part of a CMP.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (strcmp(ddi_node_name(dip), DRMACH_CPU_NAMEPROP) != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (strcmp(ddi_node_name(pdip), DRMACH_CMP_NAMEPROP) == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The branch rooted at dip will have been previously
03831d35f7499c87d51205817c93e9a8d42c4baestevel * held, or it will be the child of a CMP. In either
03831d35f7499c87d51205817c93e9a8d42c4baestevel * case, the hold acquired in e_ddi_nodeid_to_dip()
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is not needed.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ASSERT(drmach_is_cmp_child(dip) || e_ddi_branch_held(dip));
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_node_ddi_get_prop(drmach_node_t *np, char *name, void *buf, int len)
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* ARGSUSED */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_node_obp_get_prop(drmach_node_t *np, char *name, void *buf, int len)
03831d35f7499c87d51205817c93e9a8d42c4baestevel } else if (prom_getproplen(nodeid, (caddr_t)name) < 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel (void) prom_getprop(nodeid, (caddr_t)name, (caddr_t)buf);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_node_ddi_get_proplen(drmach_node_t *np, char *name, int *len)
03831d35f7499c87d51205817c93e9a8d42c4baestevel } else if (ddi_getproplen(DDI_DEV_T_ANY, ndip, DDI_PROP_DONTPASS,
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_node_obp_get_proplen(drmach_node_t *np, char *name, int *len)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_array provides convenient array construction, access,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bounds checking and array destruction logic.
03831d35f7499c87d51205817c93e9a8d42c4baestevel arr = kmem_zalloc(sizeof (drmach_array_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel arr->arr_sz = (max_index - min_index + 1) * sizeof (void *);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_array_set(drmach_array_t *arr, int idx, drmachid_t val)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /*NOTREACHED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_array_get(drmach_array_t *arr, int idx, drmachid_t *val)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /*NOTREACHED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_array_first(drmach_array_t *arr, int *idx, drmachid_t *val)
03831d35f7499c87d51205817c93e9a8d42c4baestevel while ((rv = drmach_array_get(arr, *idx, val)) == 0 && *val == NULL)
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_array_next(drmach_array_t *arr, int *idx, drmachid_t *val)
03831d35f7499c87d51205817c93e9a8d42c4baestevel while ((rv = drmach_array_get(arr, *idx, val)) == 0 && *val == NULL)
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_array_dispose(drmach_array_t *arr, void (*disposer)(drmachid_t))
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* clear the array entry */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* read the gdcd, bail if magic or ver #s are not what is expected */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (iosram_rd(GDCD_MAGIC, 0, sizeof (gdcd_t), (caddr_t)gdcd)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel * On Starcat, there is no CPU driver, so it is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * not necessary to configure any CPU nodes.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (; id; ) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * We held this branch earlier, so at a minimum its
03831d35f7499c87d51205817c93e9a8d42c4baestevel * root should still be present in the device tree.
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_configure: configuring DDI branch");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Record first failure but don't stop
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If non-NULL, fdip is returned held and must be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * released.
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = node->n_getprop(node, "name", name, OBP_MAXDRVNAME);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* every node is expected to have a name */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "dip: 0x%p: property %s",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Not a node of interest to dr - including "cmp",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * but it is in drmach_name2type[], which lets gptwocfg
03831d35f7499c87d51205817c93e9a8d42c4baestevel * driver to check if node is OBP created.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Derive a best-guess unit number from the portid value.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Some drmach_*_new constructors (drmach_pci_new, for example)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * will overwrite the prototype unum value with one that is more
03831d35f7499c87d51205817c93e9a8d42c4baestevel * appropriate for the device.
03831d35f7499c87d51205817c93e9a8d42c4baestevel (void) drmach_board_name(bnum, bp->cm.name, sizeof (bp->cm.name));
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) drmach_array_set(drmach_boards, bnum, bp);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_array_dispose(bp->devices, drmach_device_dispose);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_board_status(drmachid_t id, drmach_status_t *stat)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * we need to know if the board's connected before
03831d35f7499c87d51205817c93e9a8d42c4baestevel * issuing a showboard message. If it's connected, we just
03831d35f7499c87d51205817c93e9a8d42c4baestevel * reply with status composed of cached info
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_proto_hdr_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_mbox_trans(DRMSG_SHOWBOARD, bp->bnum, obufp,
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) strncpy(bp->type, shb.board_type, sizeof (bp->type));
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) strncpy(stat->type, shb.board_type, sizeof (stat->type));
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) snprintf(stat->info, sizeof (stat->info),
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) strncpy(stat->type, bp->type, sizeof (stat->type));
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel struct drmach_msglist *prev; /* link to previous entry */
03831d35f7499c87d51205817c93e9a8d42c4baestevel struct drmach_msglist *next; /* link to next entry */
03831d35f7499c87d51205817c93e9a8d42c4baestevel struct drmach_msglist *link; /* link to related entry */
03831d35f7499c87d51205817c93e9a8d42c4baestevelkmutex_t drmach_g_mbox_mutex; /* mutex for mailbox globals */
03831d35f7499c87d51205817c93e9a8d42c4baestevelkmutex_t drmach_ri_mbox_mutex; /* mutex for mailbox reinit */
03831d35f7499c87d51205817c93e9a8d42c4baestevelkmutex_t drmach_msglist_mutex; /* mutex for message list */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_msglist_t *drmach_msglist_first; /* first entry in msg list */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_msglist_t *drmach_msglist_last; /* last entry in msg list */
03831d35f7499c87d51205817c93e9a8d42c4baestevelkthread_t *drmach_getmsg_thread; /* ptr to getmsg thread */
03831d35f7499c87d51205817c93e9a8d42c4baestevelvolatile int drmach_getmsg_thread_run; /* run flag for getmsg thr */
03831d35f7499c87d51205817c93e9a8d42c4baestevelkmutex_t drmach_sendmsg_mutex; /* mutex for sendmsg cv */
03831d35f7499c87d51205817c93e9a8d42c4baestevelkcondvar_t drmach_sendmsg_cv; /* signaled to send new msg */
03831d35f7499c87d51205817c93e9a8d42c4baestevelkthread_t *drmach_sendmsg_thread; /* ptr to sendmsg thread */
03831d35f7499c87d51205817c93e9a8d42c4baestevelvolatile int drmach_sendmsg_thread_run; /* run flag for sendmsg */
03831d35f7499c87d51205817c93e9a8d42c4baestevelint drmach_mbox_ipending; /* set if reinit scheduled */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Timeout values (in seconds) used when waiting for replies (from the SC) to
03831d35f7499c87d51205817c93e9a8d42c4baestevel * requests that we sent. Since we only receive boardevent messages, and they
03831d35f7499c87d51205817c93e9a8d42c4baestevel * are events rather than replies, there is no boardevent timeout.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Delay (in seconds) used after receiving a non-transient error indication from
03831d35f7499c87d51205817c93e9a8d42c4baestevel * an mboxsc_getmsg call in the thread that loops waiting for incoming messages.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Timeout values (in milliseconds) for mboxsc_putmsg and mboxsc_getmsg calls.
03831d35f7499c87d51205817c93e9a8d42c4baestevelclock_t drmach_to_putmsg; /* set in drmach_mbox_init */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Normally, drmach_to_putmsg is set dynamically during initialization in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_mbox_init. This has the potentially undesirable side effect of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * clobbering any value that might have been set in /etc/system. To prevent
03831d35f7499c87d51205817c93e9a8d42c4baestevel * dynamic setting of drmach_to_putmsg (thereby allowing it to be tuned in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * /etc/system), set drmach_use_tuned_putmsg_to to 1.
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* maximum conceivable message size for future mailbox protocol versions */
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < 18; ++i) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (j = 0; j < S0_LPORT_COUNT; j++) {
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx, "
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx\n", j,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx, "
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < 18; ++i) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (j = 0; j < S0_LPORT_COUNT; j++) {
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx, "
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx\n", j,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx, "
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < 18; ++i) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (j = 0; j < S0_LPORT_COUNT; j++) {
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx, "
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx\n", j,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx, "
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "MADR[%d] = 0x%lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("dr hdr:\n\tid=0x%x vers=0x%x cmd=0x%x exp=0x%x slot=0x%x\n",
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni php->message_id, php->drproto_version, php->command,
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("\treply_status=0x%x error_code=0x%x\n", php->reply_status,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Callback function passed to taskq_dispatch when a mailbox reinitialization
03831d35f7499c87d51205817c93e9a8d42c4baestevel * handshake needs to be scheduled. The handshake can't be performed by the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * thread that determines it is needed, in most cases, so this function is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * dispatched on the system-wide taskq pool of threads. Failure is reported but
03831d35f7499c87d51205817c93e9a8d42c4baestevel * otherwise ignored, since any situation that requires a mailbox initialization
03831d35f7499c87d51205817c93e9a8d42c4baestevel * handshake will continue to request the handshake until it succeeds.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* need to initialize the mailbox */
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_proto_hdr_t), KM_SLEEP);
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "mbox_init: MBOX_INIT failed ecode=0x%x",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * To ensure sufficient compatibility with future versions of the DR mailbox
03831d35f7499c87d51205817c93e9a8d42c4baestevel * protocol, we use a buffer that is large enough to receive the largest message
03831d35f7499c87d51205817c93e9a8d42c4baestevel * that could possibly be sent to us. However, since that ends up being fairly
03831d35f7499c87d51205817c93e9a8d42c4baestevel * large, allocating it on the stack is a bad idea. Fortunately, this function
03831d35f7499c87d51205817c93e9a8d42c4baestevel * does not need to be MT-safe since it is only invoked by the mailbox
03831d35f7499c87d51205817c93e9a8d42c4baestevel * framework, which will never invoke it multiple times concurrently. Since
03831d35f7499c87d51205817c93e9a8d42c4baestevel * that is the case, we can use a static buffer.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni err = mboxsc_getmsg(KEY_SCDR, &type, &command, &transid,
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* don't try to interpret anything with the wrong version number */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((err == 0) && (msg->p_hdr.drproto_version != DRMBX_VERSION)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "mailbox version mismatch 0x%x vs 0x%x",
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* schedule a reinit handshake if one isn't pending */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "failed to schedule mailbox reinit");
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((err != 0) || (msg->p_hdr.reply_status != DRMSG_REPLY_OK)) {
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "Unsolicited mboxsc_getmsg failed: err=0x%x code=0x%x",
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* check for initialization event */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* schedule a reinit handshake if one isn't pending */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "mailbox reinit");
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* anything else will be a log_sysevent call */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * unlink an entry from the message transaction list
03831d35f7499c87d51205817c93e9a8d42c4baestevel * caller must hold drmach_msglist_mutex
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* get a reply message */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni err = mboxsc_getmsg(KEY_SCDR, &type, &command, &transid,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If mboxsc_getmsg returns ETIMEDOUT or EAGAIN, then
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the "error" is really just a normal, transient
03831d35f7499c87d51205817c93e9a8d42c4baestevel * condition and we can retry the operation right away.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Any other error suggests a more serious problem,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * ranging from a message being too big for our buffer
03831d35f7499c87d51205817c93e9a8d42c4baestevel * (EMSGSIZE) to total failure of the mailbox layer.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This second class of errors is much less "transient",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * so rather than retrying over and over (and getting
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the same error over and over) as fast as we can,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * we'll sleep for a while before retrying.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "mailbox version mismatch 0x%x vs 0x%x",
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* schedule a reinit handshake if one isn't pending */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "mailbox reinit");
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "!mbox_getmsg: no match for id 0x%x",
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "! cmd = 0x%x, exb = %d, slot = %d",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Search through the list to find entries awaiting
03831d35f7499c87d51205817c93e9a8d42c4baestevel * transmission to the SC
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni php->command, NULL, entry->o_buflen, (void *)mp,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni &drmach_sendmsg_mutex, (5 * hz), TR_CLOCK_TICK);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_msglist_new(caddr_t ibufp, uint32_t ilen, dr_proto_hdr_t *hdrp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel listp = kmem_zalloc(sizeof (drmach_msglist_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&listp->s_lock, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&listp->g_lock, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mbox_req_rply(dr_proto_hdr_t *hdrp, uint32_t olen, caddr_t ibufp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* setup transaction list entry */
03831d35f7499c87d51205817c93e9a8d42c4baestevel listp = drmach_msglist_new(ibufp, ilen, hdrp, olen, nrtry);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* send mailbox message, await reply */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni cmn_err(CE_WARN, "!mboxsc_putmsg failed: 0x%x", listp->f_error);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "! cmd = 0x%x, exb = %d, slot = %d",
03831d35f7499c87d51205817c93e9a8d42c4baestevel "!msgid=0x%x reply timed out",
03831d35f7499c87d51205817c93e9a8d42c4baestevel case 0: /* signal received */
03831d35f7499c87d51205817c93e9a8d42c4baestevel "operation interrupted by signal");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If link is set for this entry, check to see if
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the linked entry has been replied to. If not,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * wait for the response.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Currently, this is only used for ABORT_TEST functionality,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * wherein a check is made for the TESTBOARD reply when
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the ABORT_TEST reply is received.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If the reply to the linked entry hasn't been
03831d35f7499c87d51205817c93e9a8d42c4baestevel * received, clear the existing link->f_error,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and await the reply.
03831d35f7499c87d51205817c93e9a8d42c4baestevel "!link msgid=0x%x reply timed out",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If framework failure is due to signal, return "no error"
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (drerr_new(0, ESTC_NOT_ASSIGNED, "%s", a_pnt));
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni return (drerr_new(0, ESTC_TEST_IN_PROGRESS, "%s",
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (drerr_new(0, ESTC_TESTING_BUSY, "%s", a_pnt));
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (drerr_new(0, ESTC_TEST_REQUIRED, "%s", a_pnt));
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (drerr_new(0, ESTC_UNAVAILABLE, "%s", a_pnt));
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni return (drerr_new(0, ESTC_SMS_ERR_RECOVERABLE, "%s",
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni return (drerr_new(1, ESTC_SMS_ERR_UNRECOVERABLE, "%s",
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mbox_trans(uint8_t msgtype, int bnum, caddr_t obufp, int olen,
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* need to initialize the mailbox */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni cmn_err(CE_WARN, "!reinitializing DR mailbox");
03831d35f7499c87d51205817c93e9a8d42c4baestevel mlp = drmach_mbox_req_rply(&imsg, sizeof (imsg), 0, 0,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If framework failure incoming is encountered on
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the MBOX_INIT [timeout on SMS reply], the error
03831d35f7499c87d51205817c93e9a8d42c4baestevel * type must be changed before returning to caller.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This is to prevent drmach_board_connect() and
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_board_disconnect() from marking boards
03831d35f7499c87d51205817c93e9a8d42c4baestevel * UNUSABLE based on MBOX_INIT failures.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((err != NULL) && (err->e_code == ESTC_MBXRPLY)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel "!Changed mbox incoming to outgoing"
03831d35f7499c87d51205817c93e9a8d42c4baestevel " failure on reinit");
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* setup outgoing mailbox header */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni cmn_err(CE_WARN, "Unknown outgoing message type 0x%x",
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni mlp = drmach_mbox_req_rply(hdrp, olen, ibufp, ilen, timeout,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * For DRMSG_TESTBOARD attempts which have timed out, or
03831d35f7499c87d51205817c93e9a8d42c4baestevel * been aborted due to a signal received after mboxsc_putmsg()
03831d35f7499c87d51205817c93e9a8d42c4baestevel * has succeeded in sending the message, a DRMSG_ABORT_TEST
03831d35f7499c87d51205817c93e9a8d42c4baestevel * must be sent.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ((mlp->f_error == EINTR) || ((mlp->f_error == ETIMEDOUT) &&
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* register the outgoing mailbox */
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "DR - SC mboxsc_init failed: 0x%x", err);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* setup the mboxsc_putmsg timeout value */
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_NOTE, "!using tuned drmach_to_putmsg = 0x%lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* register the incoming mailbox */
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "SC - DR mboxsc_init failed: 0x%x", err);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* initialize mutex for mailbox globals */
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_g_mbox_mutex, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* initialize mutex for mailbox re-init */
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_ri_mbox_mutex, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* initialize mailbox message list elements */
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_msglist_mutex, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_sendmsg_mutex, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* start mailbox sendmsg thread */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* start mailbox getmsg thread */
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_proto_hdr_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "mbox_init: MBOX_INIT failed ecode=0x%x",
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "drmach_mbox_fini: waiting for mbox threads...");
03831d35f7499c87d51205817c93e9a8d42c4baestevel while ((drmach_getmsg_thread_run == 0) ||
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni cmn_err(CE_WARN, "drmach_mbox_fini: mbox threads done.");
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* de-register the outgoing mailbox */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* de-register the incoming mailbox */
03831d35f7499c87d51205817c93e9a8d42c4baestevel case 0: case 1: case 2: case 3: /* cpu/wci devices */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * For Starcat, we must be children of the root devinfo node
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Only children of the root devinfo node need to be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * held/released since they are the only valid targets
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of tree operations. This corresponds to the node types
03831d35f7499c87d51205817c93e9a8d42c4baestevel * listed in the drmach_name2type array.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (i < 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* Not of interest to us */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "drmach_init: failed to access GDCD\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel (void) prom_getprop(nodeid, "portid", (caddr_t)&portid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (drmach_array_get(drmach_boards, bnum, &id) == -1) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* portid translated to an invalid board number */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni " invalid property value, %s=%u",
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* clean up */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel } while ((nodeid = prom_nextnode(nodeid)) != OBP_NONODE);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_cpu_sram_va = vmem_alloc(heap_arena, PAGESIZE, VM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (gdcd->dcd_testcage_log2_mbytes_size != DCD_DR_TESTCAGE_DISABLED) {
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni 1 << (gdcd->dcd_testcage_log2_mbytes_size + 20);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_iocage_vaddr = (caddr_t)vmem_alloc(heap_arena,
03831d35f7499c87d51205817c93e9a8d42c4baestevel hat_devload(kas.a_hat, drmach_iocage_vaddr, drmach_iocage_size,
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_array_dispose(drmach_boards, drmach_board_dispose);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "drmach_init: iocage not available\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_iocage_lock, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_xt_mb_lock, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_bus_sync_lock, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel mutex_init(&drmach_slice_table_lock, NULL, MUTEX_DRIVER, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "DR - SC mailbox initialization Failed");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk immediate children of devinfo root node and hold
03831d35f7499c87d51205817c93e9a8d42c4baestevel * all devinfo branches of interest.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ddi_walk_devs(ddi_get_child(rdip), hold_rele_branch, &hold);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * To avoid a circular patch dependency between DR and AXQ, the AXQ
03831d35f7499c87d51205817c93e9a8d42c4baestevel * rev introducing the axq_iopause_*_all interfaces should not regress
03831d35f7499c87d51205817c93e9a8d42c4baestevel * when installed without the DR rev using those interfaces. The default
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is for iopause to be enabled/disabled during axq suspend/resume. By
03831d35f7499c87d51205817c93e9a8d42c4baestevel * setting the following axq flag to zero, axq will not enable iopause
03831d35f7499c87d51205817c93e9a8d42c4baestevel * during suspend/resume, instead DR will call the axq_iopause_*_all
03831d35f7499c87d51205817c93e9a8d42c4baestevel * interfaces during drmach_copy_rename.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_array_dispose(drmach_boards, drmach_board_dispose);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk immediate children of the root devinfo node
03831d35f7499c87d51205817c93e9a8d42c4baestevel * releasing holds acquired on branches in drmach_init()
03831d35f7499c87d51205817c93e9a8d42c4baestevel ddi_walk_devs(ddi_get_child(rdip), hold_rele_branch, &hold);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_read_madr(drmach_mem_t *mp, int bank, uint64_t *madr)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* get register address, read madr value */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (STARCAT_CPUID_TO_PORTID(CPU->cpu_id) == mp->dev.portid) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_mem_t *mp, uint64_t current_basepa, uint64_t new_basepa)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* fetch mc's bank madr register value */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* encode new base pa into madr */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (p);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_prep_schizo_script(uint64_t *p, drmach_mem_t *mp, uint64_t new_basepa)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* memory is always in slot 0 */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* look up slot 1 board on same expander */
03831d35f7499c87d51205817c93e9a8d42c4baestevel idx = DRMACH_EXPSLOT2BNUM(DRMACH_BNUM2EXP(mp->dev.bp->bnum), 1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* look up should never be out of bounds */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* nothing to do when board is not found or has no devices */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (p);
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Skip all non-Schizo IO devices (only IO nodes
03831d35f7499c87d51205817c93e9a8d42c4baestevel * that are Schizo devices have non-zero scsr_pa).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Filter out "other" leaf to avoid writing to the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * same Schizo Control/Status Register twice.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (p);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * For Panther MCs, append the MC idle reg address and drmach_mem_t pointer.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The latter is returned when drmach_rename fails to idle a Panther MC and
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is used to identify the MC for error reporting.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_prep_pn_mc_idle(uint64_t *p, drmach_mem_t *mp, int local)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* only slot 0 has memory */
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (mp = mp->dev.bp->mem; mp != NULL; mp = mp->next) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (mp->dev.portid == STARCAT_CPUID_TO_PORTID(CPU->cpu_id)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel } else if (!local) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (p);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_prep_rename_script(drmach_mem_t *s_mp, drmach_mem_t *t_mp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* verify supplied buffer space is adequate */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* addr for all possible MC banks */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* list section terminator */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* addr/id tuple for local Panther MC idle reg */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* list section terminator */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* addr/id tuple for 2 boards with 4 Panther MC idle regs */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* list section terminator */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* addr/val tuple for 1 proc with 4 MC banks */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* list section terminator */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* addr/val tuple for 2 boards w/ 2 schizos each */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* addr/val tuple for 2 boards w/ 16 MC banks each */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* list section terminator */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* addr/val tuple for 18 AXQs w/ two slots each */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* list section terminator */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni /* list terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* copy bank list to rename script */
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (q = drmach_bus_sync_list; *q; q++, p++)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* list section terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Write idle script for MC on this processor. A script will be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * produced only if this is a Panther processor on the source or
03831d35f7499c87d51205817c93e9a8d42c4baestevel * target board.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* list section terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Write idle script for all other MCs on source and target
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Panther boards.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* list section terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Step 1: Write source base address to target MC
03831d35f7499c87d51205817c93e9a8d42c4baestevel * with present bit off.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Step 2: Now rewrite target reg with present bit on.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* exchange base pa. include slice offset in new target base pa */
03831d35f7499c87d51205817c93e9a8d42c4baestevel s_new_basepa = t_basepa & ~ (DRMACH_MEM_SLICE_SIZE - 1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel t_new_basepa = (s_basepa & ~ (DRMACH_MEM_SLICE_SIZE - 1)) +
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("preparing MC MADR rename script (master is CPU%d):\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Write rename script for MC on this processor. A script will
03831d35f7499c87d51205817c93e9a8d42c4baestevel * be produced only if this processor is on the source or target
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (mp->dev.portid == STARCAT_CPUID_TO_PORTID(CPU->cpu_id)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (mp->dev.portid == STARCAT_CPUID_TO_PORTID(CPU->cpu_id)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* list section terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Write rename script for all other MCs on source and target
03831d35f7499c87d51205817c93e9a8d42c4baestevel p = drmach_prep_mc_rename(p, 0, mp, s_basepa, s_new_basepa);
03831d35f7499c87d51205817c93e9a8d42c4baestevel p = drmach_prep_mc_rename(p, 0, mp, t_basepa, t_new_basepa);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* Write rename script for Schizo LPA_BASE/LPA_BND */
03831d35f7499c87d51205817c93e9a8d42c4baestevel p = drmach_prep_schizo_script(p, s_mp, s_new_basepa);
03831d35f7499c87d51205817c93e9a8d42c4baestevel p = drmach_prep_schizo_script(p, t_mp, t_new_basepa);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* list section terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("preparing AXQ CASM rename script (EXP%d <> EXP%d):\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* list section & final terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* paranoia */
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (*q) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* skip terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("local Panther MC idle reg (via ASI 0x4a):\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (*q) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* skip terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("non-local Panther MC idle reg (via ASI 0x15):\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (*q) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* skip terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("MC reprogramming script (via ASI 0x72):\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (*q) {
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki r, v, (long)(DRMACH_MC_UM_TO_PA(v)|
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* skip terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (*q) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* skip terminator */
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (*q) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* verify final terminator is present */
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void *)buf, (int)((intptr_t)p - (intptr_t)buf));
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_prep_xt_mb_for_slice_update(drmach_board_t *bp, uchar_t slice)
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel (void *) &s1bp);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_copy_rename_init(drmachid_t t_id, uint64_t t_slice_offset,
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmachid_t s_id, struct memlist *c_ml, drmachid_t *cr_id)
03831d35f7499c87d51205817c93e9a8d42c4baestevel extern void drmach_rename(uint64_t *, uint_t *, uint64_t *);
03831d35f7499c87d51205817c93e9a8d42c4baestevel extern void drmach_rename_end(void);
03831d35f7499c87d51205817c93e9a8d42c4baestevel uint64_t off_mask, s_copybasepa, t_copybasepa, t_basepa;
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* get starting physical address of target memory */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* calculate slice offset mask from slice size */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* calculate source and target base pa */
56f33205c9ed776c3c909e07d52e94610a675740Jonathan Adams t_basepa + ((c_ml->ml_address & off_mask) - t_slice_offset);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* paranoia */
56f33205c9ed776c3c909e07d52e94610a675740Jonathan Adams ASSERT((c_ml->ml_address & off_mask) >= t_slice_offset);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* adjust copy memlist addresses to be relative to copy base pa */
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("source copy span: base pa 0x%lx, end pa 0x%lx\n",
56f33205c9ed776c3c909e07d52e94610a675740Jonathan Adams s_copybasepa + x_ml->ml_address + x_ml->ml_size);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("target copy span: base pa 0x%lx, end pa 0x%lx\n",
56f33205c9ed776c3c909e07d52e94610a675740Jonathan Adams t_copybasepa + x_ml->ml_address + x_ml->ml_size);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("copy memlist (relative to copy base pa):\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("current source base pa 0x%lx, size 0x%lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("current target base pa 0x%lx, size 0x%lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif /* DEBUG */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* Map in appropriate cpu sram page */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* Make sure the rename routine will fit */
03831d35f7499c87d51205817c93e9a8d42c4baestevel len = (ptrdiff_t)drmach_rename_end - (ptrdiff_t)drmach_rename;
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* copy text. standard bcopy not designed to work in nc space */
03831d35f7499c87d51205817c93e9a8d42c4baestevel *p++ = *q++;
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* zero remainder. standard bzero not designed to work in nc space */
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki DRMACH_PR("drmach_rename function 0x%p, len %d\n", (void *)wp, len);
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni err = drmach_prep_rename_script(s_mp, t_mp, t_slice_offset, wp,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni (uint64_t)drmach_cpu_sram_va, (uint64_t)ksfmmup);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* disable and flush CDC */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* mark both memory units busy */
03831d35f7499c87d51205817c93e9a8d42c4baestevel cr = vmem_alloc(static_alloc_arena, sizeof (drmach_copy_rename_t),
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (DRMACH_L1_SET_LPA(s_mp->dev.bp) && drmach_reprogram_lpa) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (DRMACH_L1_SET_LPA(t_mp->dev.bp) && drmach_reprogram_lpa) {
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni (uint64_t)drmach_cpu_sram_va, (uint64_t)ksfmmup);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "failed to idle memory controller %s on %s: "
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drerr_new(0, ESBD_SUSPEND, "EX%d", (uintptr_t)cr->earg);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "failed to idle EX%ld AXQ slot1 activity prior"
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "copy-rename aborted due to uncorrectable "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "memory error");
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "unknown copy-rename error code (%d)\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_L1_SET_LPA(cr->t_mp->dev.bp)) && drmach_reprogram_lpa) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < NCPU; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* update casm shadow for target and source board */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Make a good-faith effort to notify the SC about the copy-rename, but
03831d35f7499c87d51205817c93e9a8d42c4baestevel * don't worry if it fails, since a subsequent claim/unconfig/unclaim
03831d35f7499c87d51205817c93e9a8d42c4baestevel * will duplicate the update.
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_mbox_msg_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_msg_memslice_init(obufp->msgdata.dm_uc.mem_slice);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_msg_memregs_init(obufp->msgdata.dm_uc.mem_regs);
03831d35f7499c87d51205817c93e9a8d42c4baestevel (void) drmach_mbox_trans(DRMSG_UNCONFIG, cr->s_mp->dev.bp->bnum,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni (caddr_t)obufp, sizeof (dr_mbox_msg_t), (caddr_t)NULL, 0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel vmem_free(static_alloc_arena, cr, sizeof (drmach_copy_rename_t));
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("waited %d out of %d tries for drmach_rename_wait on %d cpus",
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni drmach_rename_ntries, drmach_cpu_ntries, drmach_rename_count);
03831d35f7499c87d51205817c93e9a8d42c4baestevel xcfunc_t *drmach_end_wait_xcall = drmach_rename_done;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Prevent slot1 IO from accessing Safari memory bus.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < drmach_cpu_ntries; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < NCPU; i++) /* steal the line back, preserve data */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* disable CE reporting */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* disable interrupts (paranoia) */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Execute copy-rename under on_trap to protect against a panic due
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to an uncorrectable error. Instead, DR will abort the copy-rename
03831d35f7499c87d51205817c93e9a8d42c4baestevel * operation and rely on the OS to do the error reporting.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * In general, trap handling on any cpu once the copy begins
03831d35f7499c87d51205817c93e9a8d42c4baestevel * can result in an inconsistent memory image on the target.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* copy 32 bytes at src_pa to dst_pa */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* increment by 32 bytes */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* decrement by 32 bytes */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX CHEETAH SUPPORT
03831d35f7499c87d51205817c93e9a8d42c4baestevel * For cheetah, we need to grab the iocage lock since iocage
03831d35f7499c87d51205817c93e9a8d42c4baestevel * memory is used for e$ flush.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * NOTE: This code block is dangerous at this point in the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * copy-rename operation. It modifies memory after the copy
03831d35f7499c87d51205817c93e9a8d42c4baestevel * has taken place which means that any persistent state will
03831d35f7499c87d51205817c93e9a8d42c4baestevel * be abandoned after the rename operation. The code is also
03831d35f7499c87d51205817c93e9a8d42c4baestevel * performing thread synchronization at a time when all but
03831d35f7499c87d51205817c93e9a8d42c4baestevel * one processors are paused. This is a potential deadlock
03831d35f7499c87d51205817c93e9a8d42c4baestevel * situation.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This code block must be moved to drmach_copy_rename_init.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bcopy32_il is implemented as a series of ldxa/stxa via
03831d35f7499c87d51205817c93e9a8d42c4baestevel * ASI_MEM instructions. Following the copy loop, the E$
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of the master (this) processor will have lines in state
03831d35f7499c87d51205817c93e9a8d42c4baestevel * O that correspond to lines of home memory in state gI.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * An E$ flush is necessary to commit these lines before
03831d35f7499c87d51205817c93e9a8d42c4baestevel * proceeding with the rename operation.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Flushing the E$ will automatically flush the W$, but
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the D$ and I$ must be flushed separately and explicitly.
03831d35f7499c87d51205817c93e9a8d42c4baestevel flush_ecache_il(caddr, csize, lnsize); /* inline version */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Each line of home memory is now in state gM, except in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the case of a cheetah processor when the E$ flush area
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is included within the copied region. In such a case,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the lines of home memory for the upper half of the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * flush area are in state gS.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Each line of target memory is in state gM.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Each line of this processor's E$ is in state I, except
03831d35f7499c87d51205817c93e9a8d42c4baestevel * those of a cheetah processor. All lines of a cheetah
03831d35f7499c87d51205817c93e9a8d42c4baestevel * processor's E$ are in state S and correspond to the lines
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in upper half of the E$ flush area.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * It is vital at this point that none of the lines in the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * home or target memories are in state gI and that none
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of the lines in this processor's E$ are in state O or Os.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * A single instance of such a condition will cause loss of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * coherency following the rename operation.
03831d35f7499c87d51205817c93e9a8d42c4baestevel (*(void(*)())drmach_cpu_sram_va)(cr->data, &cr->ecode, &cr->earg);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Rename operation complete. The physical address space
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of the home and target memories have been swapped, the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * routing data in the respective CASM entries have been
03831d35f7499c87d51205817c93e9a8d42c4baestevel * swapped, and LPA settings in the processor and schizo
03831d35f7499c87d51205817c93e9a8d42c4baestevel * devices have been reprogrammed accordingly.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * In the case of a cheetah processor, the E$ remains
03831d35f7499c87d51205817c93e9a8d42c4baestevel * populated with lines in state S that correspond to the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * lines in the former home memory. Now that the physical
03831d35f7499c87d51205817c93e9a8d42c4baestevel * addresses have been swapped, these E$ lines correspond
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to lines in the new home memory which are in state gM.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This combination is invalid. An additional E$ flush is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * necessary to restore coherency. The E$ flush will cause
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the lines of the new home memory for the flush region
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to transition from state gM to gS. The former home memory
03831d35f7499c87d51205817c93e9a8d42c4baestevel * remains unmodified. This additional E$ flush has no effect
03831d35f7499c87d51205817c93e9a8d42c4baestevel * on a cheetah+ processor.
03831d35f7499c87d51205817c93e9a8d42c4baestevel flush_ecache_il(caddr, csize, lnsize); /* inline version */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The D$ and I$ must be flushed to ensure that coherency is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * maintained. Any line in a cache that is in the valid
03831d35f7499c87d51205817c93e9a8d42c4baestevel * state has its corresponding line of the new home memory
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in the gM state. This is an invalid condition. When the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * flushes are complete the cache line states will be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * resynchronized with those in the new home memory.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* enable interrupts */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* enable CE reporting */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX CHEETAH SUPPORT
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic sbd_error_t *drmach_io_status(drmachid_t, drmach_status_t *);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_pci_new(drmach_device_t *proto, drmachid_t *idp)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* pci nodes are expected to have regs */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "Device Node 0x%x: property %s",
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = node->n_getprop(node, "reg", (void *)regs, sizeof (regs));
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "Device Node 0x%x: property %s",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Fix up unit number so that Leaf A has a lower unit number
03831d35f7499c87d51205817c93e9a8d42c4baestevel * than Leaf B.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* reassemble 64-bit base address */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_io_new(drmach_device_t *proto, drmachid_t *idp)
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) snprintf(ip->dev.cm.name, sizeof (ip->dev.cm.name), "%s%d",
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_pre_op(int cmd, drmachid_t id, drmach_opts_t *opts)
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_post_op(int cmd, drmachid_t id, drmach_opts_t *opts)
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (drmach_array_get(drmach_boards, bnum, id) == -1) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_proto_hdr_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_board_non_panther_cpus(gdcd_t *gdcd, uint_t exp, uint_t slot)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Determine PRD port indices based on slot location.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* check all */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (gdcd->dcd_prd[exp][port].prd_ptype == SAFPTYPE_CPU &&
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This Safari port passed POST and represents a
03831d35f7499c87d51205817c93e9a8d42c4baestevel * cpu, so check the implementation.
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_board_non_panther_cpus: exp=%d, slot=%d, "
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_board_connect(drmachid_t id, drmach_opts_t *opts)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Build the casm info portion of the CLAIM message.
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_mbox_msg_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_msg_memslice_init(obufp->msgdata.dm_cr.mem_slice);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_msg_memregs_init(obufp->msgdata.dm_cr.mem_regs);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_mbox_trans(DRMSG_CLAIM, bp->bnum, (caddr_t)obufp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * if mailbox timeout or unrecoverable error from SC,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * board cannot be touched. Mark the status as
03831d35f7499c87d51205817c93e9a8d42c4baestevel * unusable.
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "failed to read GDCD info for %s\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Read CPU SRAM DR buffer offset from GDCD.
03831d35f7499c87d51205817c93e9a8d42c4baestevel gdcd->dcd_slot[exp][slot].l1ss_cpu_drblock_xwd_offset << 3;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Read board LPA setting from GDCD.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX Until the Solaris large pages support heterogeneous cpu
03831d35f7499c87d51205817c93e9a8d42c4baestevel * domains, DR needs to prevent the addition of non-Panther cpus
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to an all-Panther domain with large pages enabled.
03831d35f7499c87d51205817c93e9a8d42c4baestevel panther_pages_enabled = (page_num_pagesizes() > DEFAULT_MMU_PAGE_SIZES);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (drmach_board_non_panther_cpus(gdcd, exp, slot) > 0 &&
03831d35f7499c87d51205817c93e9a8d42c4baestevel panther_pages_enabled && drmach_large_page_restriction) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "Domain shutdown is required to add a non-"
03831d35f7499c87d51205817c93e9a8d42c4baestevel "UltraSPARC-IV+ board into an all UltraSPARC-IV+ domain");
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* do saf configurator stuff */
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("calling sc_probe_board for bnum=%d\n", bp->bnum);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* flush CDC srams */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Build the casm info portion of the UNCLAIM message.
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_mbox_msg_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_msg_memslice_init(obufp->msgdata.dm_ur.mem_slice);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_msg_memregs_init(obufp->msgdata.dm_ur.mem_regs);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * we clear the connected flag just in case it would have
03831d35f7499c87d51205817c93e9a8d42c4baestevel * been set by a concurrent drmach_board_status() thread
03831d35f7499c87d51205817c93e9a8d42c4baestevel * before the UNCLAIM completed.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Now that the board has been successfully attached, obtain
03831d35f7499c87d51205817c93e9a8d42c4baestevel * platform-specific DIMM serial id information for the board.
03831d35f7499c87d51205817c93e9a8d42c4baestevel plat_ecc_capability_sc_get(PLAT_ECC_DIMM_SID_MESSAGE)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel (void) plat_request_mem_sids(DRMACH_BNUM2EXP(bp->bnum));
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_slice_table_update(drmach_board_t *bp, int invalidate)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* invalidate cached casm value */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* invalidate cached axq info if for same exp */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (axq_dip == NULL || !i_ddi_devi_attached(axq_dip)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* search for an attached slot0 axq instance */
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < AXQ_MAX_EXP * AXQ_MAX_SLOT_PER_EXP; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel "instance %d\n", i);
03831d35f7499c87d51205817c93e9a8d42c4baestevel break; /* found */
03831d35f7499c87d51205817c93e9a8d42c4baestevel "update axq dip\n");
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni DRMACH_PR("using AXQ casm %d.%d for slot%d.%d\n", axq_exp, axq_slot,
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* invalidate entry */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * find a slice that routes to expander e. If no match
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is found, drmach_slice_table[e] will remain invalid.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The CASM is a routing table indexed by slice number.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Each element in the table contains permission bits,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * a destination expander number and a valid bit. The
03831d35f7499c87d51205817c93e9a8d42c4baestevel * valid bit must true for the element to be meaningful.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CASM entry structure
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Bits 15..6 ignored
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Bit 5 valid
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Bits 0..4 expander number
03831d35f7499c87d51205817c93e9a8d42c4baestevel * NOTE: the for loop is really enumerating the range of slices,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * which is ALWAYS equal to the range of expanders. Hence,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * AXQ_MAX_EXP is okay to use in this loop.
03831d35f7499c87d51205817c93e9a8d42c4baestevel uint32_t casm = axq_casm_read(axq_exp, axq_slot, slice);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Get base and bound PAs for slot 1 board lpa programming
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If a cpu/mem board is present in the same expander, use slice
03831d35f7499c87d51205817c93e9a8d42c4baestevel * information corresponding to the CASM. Otherwise, set base and
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bound PAs to 0.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_lpa_bb_get(drmach_board_t *s1bp, uint64_t *basep, uint64_t *boundp)
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (drmach_array_get(drmach_boards, s1bp->bnum - 1, &s0id) == 0 &&
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni if ((slice = drmach_slice_table[DRMACH_BNUM2EXP(s1bp->bnum)])
03831d35f7499c87d51205817c93e9a8d42c4baestevel *basep = DRMACH_SLICE_TO_PA(slice & DRMACH_SLICE_MASK);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Reprogram slot 1 lpa's as required.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The purpose of this routine is maintain the LPA settings of the devices
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in slot 1. To date we know Schizo and Cheetah are the only devices that
03831d35f7499c87d51205817c93e9a8d42c4baestevel * require this attention. The LPA setting must match the slice field in the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CASM element for the local expander. This field is guaranteed to be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * programmed in accordance with the cacheable address space on the slot 0
03831d35f7499c87d51205817c93e9a8d42c4baestevel * board of the local expander. If no memory is present on the slot 0 board,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * there is no cacheable address space and, hence, the CASM slice field will
03831d35f7499c87d51205817c93e9a8d42c4baestevel * be zero or its valid bit will be false (or both).
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_array_get(drmach_boards, bp->bnum + 1, &id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* nothing to do when board is not found or has no devices */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (rv == -1 || s1bp == NULL || s1bp->devices == NULL) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_...lpa_set: bnum=%d base=0x%lx bound=0x%lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Skip all non-Schizo IO devices (only IO nodes
03831d35f7499c87d51205817c93e9a8d42c4baestevel * that are Schizo devices have non-zero scsr_pa).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Filter out "other" leaf to avoid writing to the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * same Schizo Control/Status Register twice.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (is_maxcat && DRMACH_L1_SET_LPA(s1bp) && drmach_reprogram_lpa) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check for unconfigured or powered-off
03831d35f7499c87d51205817c93e9a8d42c4baestevel * MCPUs. If CPU_READY flag is clear, the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * MCPU cannot be xcalled.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX CHEETAH SUPPORT
03831d35f7499c87d51205817c93e9a8d42c4baestevel * for cheetah, we need to clear iocage
03831d35f7499c87d51205817c93e9a8d42c4baestevel * memory since it will be used for e$ flush
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in drmach_set_lpa.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_slice_table[*]
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 5 valid
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 0:4 slice number
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_xt_mb[*] format for drmach_set_lpa
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 7 valid
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 6 set null LPA
03831d35f7499c87d51205817c93e9a8d42c4baestevel * (overrides bits 0:4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 0:4 slice number
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_set_lpa derives processor CBASE and
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CBND from bits 6 and 0:4 of drmach_xt_mb.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If bit 6 is set, then CBASE = CBND = 0.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Otherwise, CBASE = slice number;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CBND = slice number + 1.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * No action is taken if bit 7 is zero.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX CHEETAH SUPPORT
03831d35f7499c87d51205817c93e9a8d42c4baestevel * for cheetah, we need to clear iocage
03831d35f7499c87d51205817c93e9a8d42c4baestevel * memory since it was used for e$ flush
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in performed drmach_set_lpa.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return the number of connected Panther boards in the domain.
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_array_first(drmach_boards, &b_idx, &b_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_array_next(drmach_boards, &b_idx, &b_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_board_disconnect(drmachid_t id, drmach_opts_t *opts)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Build the casm info portion of the UNCLAIM message.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This must be done prior to calling for saf configurator
03831d35f7499c87d51205817c93e9a8d42c4baestevel * deprobe, to ensure that the associated axq instance
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is not detached.
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_mbox_msg_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_msg_memslice_init(obufp->msgdata.dm_ur.mem_slice);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If disconnecting slot 0 board, update the casm slice table
03831d35f7499c87d51205817c93e9a8d42c4baestevel * info now, for use by drmach_slot1_lpa_set()
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_msg_memregs_init(obufp->msgdata.dm_ur.mem_regs);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Update LPA information for slot1 board
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* disable and flush CDC */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * call saf configurator for deprobe
03831d35f7499c87d51205817c93e9a8d42c4baestevel * It's done now before sending an UNCLAIM message because
03831d35f7499c87d51205817c93e9a8d42c4baestevel * IKP will probe boards it doesn't know about <present at boot>
03831d35f7499c87d51205817c93e9a8d42c4baestevel * prior to unprobing them. If this happens after sending the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * UNCLAIM, it will cause a dstop for domain transgression error.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If disconnecting a board from a Panther domain, wait a fixed-
03831d35f7499c87d51205817c93e9a8d42c4baestevel * time delay for pending Safari transactions to complete on the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * disconnecting board's processors. The bus sync list read used
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in drmach_shutdown_asm to synchronize with outstanding Safari
03831d35f7499c87d51205817c93e9a8d42c4baestevel * transactions assumes no read-bypass-write mode for all memory
03831d35f7499c87d51205817c93e9a8d42c4baestevel * controllers. Since Panther supports read-bypass-write, a
03831d35f7499c87d51205817c93e9a8d42c4baestevel * delay is used that is slightly larger than the maximum Safari
03831d35f7499c87d51205817c93e9a8d42c4baestevel * timeout value in the Safari/Fireplane Config Reg.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (drmach_panther_boards() > 0 || drmach_unclaim_delay_all) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("delayed %ld ticks (%ld secs) before disconnecting "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "board %s from domain\n", stime, stime / hz, bp->cm.name);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_mbox_trans(DRMSG_UNCLAIM, bp->bnum, (caddr_t)obufp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * if mailbox timeout or unrecoverable error from SC,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * board cannot be touched. Mark the status as
03831d35f7499c87d51205817c93e9a8d42c4baestevel * unusable.
03831d35f7499c87d51205817c93e9a8d42c4baestevel "sc_probe_board failed for bnum=%d",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Now that the board has been successfully detached,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * discard platform-specific DIMM serial id information
03831d35f7499c87d51205817c93e9a8d42c4baestevel * for the board.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (np->n_getprop(np, "portid", &portid, sizeof (portid)) == 0)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Get the device_type property to see if we should
03831d35f7499c87d51205817c93e9a8d42c4baestevel * continue processing this node.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (np->n_getprop(np, "device_type", &type, sizeof (type)) != 0)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If the device is a CPU without a 'portid' property,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * it is a CMP core. For such cases, the parent node
03831d35f7499c87d51205817c93e9a8d42c4baestevel * has the portid.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (pp.n_getprop(&pp, "portid", &portid, sizeof (portid)) == 0)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This is a helper function to determine if a given
03831d35f7499c87d51205817c93e9a8d42c4baestevel * node should be considered for a dr operation according
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to predefined dr type nodes and the node's name.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Formal Parameter : The name of a device node.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return Value: -1, name does not map to a valid dr type.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * A value greater or equal to 0, name is a valid dr type.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Determine how many possible types are currently supported
03831d35f7499c87d51205817c93e9a8d42c4baestevel ntypes = sizeof (drmach_name2type) / sizeof (drmach_name2type[0]);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* Determine if the node's name correspond to a predefined type. */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* The node is an allowed type for dr. */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If the name of the node does not map to any of the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * types in the array drmach_name2type then the node is not of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * interest to dr.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_board_find_devices_cb(drmach_node_walk_args_t *args)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * if the node does not have a portid property, then
03831d35f7499c87d51205817c93e9a8d42c4baestevel * by that information alone it is known that drmach
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is not interested in it.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = node->n_getprop(node, "name", name, OBP_MAXDRVNAME);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* The node must have a name */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Ignore devices whose portid do not map to this board,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * or that their name property is not mapped to a valid
03831d35f7499c87d51205817c93e9a8d42c4baestevel * dr device name.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Create a device data structure from this node data.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The call may yield nothing if the node is not of interest
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to drmach.
03831d35f7499c87d51205817c93e9a8d42c4baestevel data->err = drmach_device_new(node, obj, portid, &id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel else if (!id) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_device_new examined the node we passed in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and determined that it was either one not of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * interest to drmach or the PIM dr layer.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * So, it is skipped.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_array_set(obj->devices, data->ndevs++, id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%d %s %d %p\n", portid, device->type, device->unum, id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("ndevs = %d dip/node = %p", data->ndevs, node->here);
03831d35f7499c87d51205817c93e9a8d42c4baestevel data->err = (*data->found)(data->a, device->type, device->unum, id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel sbd_error_t *(*found)(void *a, const char *, int, drmachid_t))
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_node_walk(bp->tree, &data, drmach_board_find_devices_cb);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_array_dispose(bp->devices, drmach_device_dispose);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_proto_hdr_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_mbox_trans(DRMSG_SHOWBOARD, bnum, obufp,
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) snprintf(buf, buflen, "%s%d", DRMACH_BNUM2SLOT(bnum) ?
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_proto_hdr_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_mbox_trans(DRMSG_POWEROFF, bp->bnum, obufp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_proto_hdr_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_mbox_trans(DRMSG_POWERON, bp->bnum, obufp,
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_board_test(drmachid_t id, drmach_opts_t *opts, int force)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If the board is an I/O or MAXCAT board, setup I/O cage for
03831d35f7499c87d51205817c93e9a8d42c4baestevel * testing. Slot 1 indicates I/O or MAXCAT board.
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_mbox_msg_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((opts->size > 0) && ((copts = opts->copts) != NULL)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel cpylen = (opts->size > DR_HPOPTLEN ? DR_HPOPTLEN : opts->size);
03831d35f7499c87d51205817c93e9a8d42c4baestevel bcopy(copts, obufp->msgdata.dm_tb.hpost_opts, cpylen);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_iocage_setup(&obufp->msgdata.dm_tb, dp, oflags);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_mbox_trans(DRMSG_TESTBOARD, bp->bnum, (caddr_t)obufp,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni sizeof (dr_mbox_msg_t), (caddr_t)&tbr, sizeof (tbr));
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((!err) && (tbr.test_status != DR_TEST_STATUS_PASSED)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* examine test status */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni err = drerr_new(0, ESTC_TEST_IN_PROGRESS, NULL);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If I/O cage test was performed, check for availability of the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * cpu used. If cpu has been returned, it's OK to proceed with
03831d35f7499c87d51205817c93e9a8d42c4baestevel * reconfiguring it for use.
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_board_test: tbr.cpu_recovered: %d",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check the cpu_recovered flag in the testboard reply, or
03831d35f7499c87d51205817c93e9a8d42c4baestevel * if the testboard request message was not sent to SMS due
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to an mboxsc_putmsg() failure, it's OK to recover the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * cpu since hpost hasn't touched it.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl for (i = 0; i < MAX_CORES_PER_CMP; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel "after I/O cage test: cpu_recovered=%d, "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "returned portid=%d",
03831d35f7499c87d51205817c93e9a8d42c4baestevel obufp = kmem_zalloc(sizeof (dr_proto_hdr_t), KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel err = drmach_mbox_trans(DRMSG_UNASSIGN, bp->bnum, obufp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (drmach_array_set(drmach_boards, bp->bnum, 0) != 0)
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_read_reg_addr(drmach_device_t *dp, uint64_t *p)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If the node does not have a portid property,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * it represents a CMP device. For a CMP, the reg
03831d35f7499c87d51205817c93e9a8d42c4baestevel * property of the parent holds the information of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * interest.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (dp->node->n_getproplen(dp->node, "portid", &len) != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (np->n_getprop(np, "reg", ®, sizeof (reg)) != 0)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* reassemble 64-bit base address */
03831d35f7499c87d51205817c93e9a8d42c4baestevel *p = ((uint64_t)reg.reg_addr_hi << 32) | reg.reg_addr_lo;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * A return value of 1 indicates success and 0 indicates a failure
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Confirm cpu was in ready set when xc was issued.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This is done by verifying rv which is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * set to 0x1 when xc_one is successful.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_cpu_read_cpuid(drmach_cpu_t *cp, processorid_t *cpuid)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If a CPU does not have a portid property, it must
03831d35f7499c87d51205817c93e9a8d42c4baestevel * be a CMP device with a cpuid property.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (np->n_getprop(np, "portid", cpuid, sizeof (*cpuid)) != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (np->n_getprop(np, "cpuid", cpuid, sizeof (*cpuid)) != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* Starcat CMP core id is bit 2 of the cpuid */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_cpu_new(drmach_device_t *proto, drmachid_t *idp)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Init the board cpu type. Assumes all board cpus are the same type.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX CHEETAH SUPPORT
03831d35f7499c87d51205817c93e9a8d42c4baestevel * determine if the domain uses Cheetah procs
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Initialize TTE for mapping CPU SRAM STARDRB buffer.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The STARDRB buffer (16KB on Cheetah+ boards, 32KB on
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Jaguar/Panther boards) is shared by all cpus in a Safari port
03831d35f7499c87d51205817c93e9a8d42c4baestevel * pair. Each cpu uses 8KB according to the following layout:
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Page 0: even numbered Cheetah+'s and Panther/Jaguar core 0's
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Page 1: odd numbered Cheetah+'s and Panther/Jaguar core 0's
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Page 2: even numbered Panther/Jaguar core 1's
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Page 3: odd numbered Panther/Jaguar core 1's
03831d35f7499c87d51205817c93e9a8d42c4baestevel cpu_stardrb_offset = cp->dev.bp->stardrb_offset + (PAGESIZE * idx);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cpu_sram_pa = DRMACH_CPU_SRAM_ADDR + cpu_stardrb_offset;
03831d35f7499c87d51205817c93e9a8d42c4baestevel ASSERT(drmach_cpu_sram_tte[cp->cpuid].tte_inthi == 0 &&
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_cpu_sram_tte[cp->cpuid].tte_inthi = TTE_PFN_INTHI(pfn) |
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_cpu_sram_tte[cp->cpuid].tte_intlo = TTE_PFN_INTLO(pfn) |
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_cpu_new: cpuid=%d, coreid=%d, stardrb_offset=0x%lx, "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "cpu_sram_offset=0x%lx, idx=%d\n", cp->cpuid, cp->coreid,
03831d35f7499c87d51205817c93e9a8d42c4baestevel cp->dev.bp->stardrb_offset, cpu_stardrb_offset, idx);
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) snprintf(cp->dev.cm.name, sizeof (cp->dev.cm.name), "%s%d",
03831d35f7499c87d51205817c93e9a8d42c4baestevel extern void restart_other_cpu(int);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * NOTE: restart_other_cpu pauses cpus during the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * slave cpu start. This helps to quiesce the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bus traffic a bit which makes the tick sync
03831d35f7499c87d51205817c93e9a8d42c4baestevel * routine in the prom more robust.
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_PANIC, "prom_hotaddcpu() for cpuid=%d failed.",
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_array_get(drmach_boards, bnum, (drmachid_t)&bp);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_cpu_start: cannot read board info for "
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki "cpuid=%d: rv=%d, bp=%p\n", cpuid, rv, (void *)bp);
03831d35f7499c87d51205817c93e9a8d42c4baestevel } else if (DRMACH_L1_SET_LPA(bp) && drmach_reprogram_lpa) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_slice_table[*]
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 5 valid
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 0:4 slice number
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_xt_mb[*] format for drmach_set_lpa
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 7 valid
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 6 set null LPA (overrides bits 0:4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit 0:4 slice number
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_set_lpa derives processor CBASE and CBND
03831d35f7499c87d51205817c93e9a8d42c4baestevel * from bits 6 and 0:4 of drmach_xt_mb. If bit 6 is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * set, then CBASE = CBND = 0. Otherwise, CBASE = slice
03831d35f7499c87d51205817c93e9a8d42c4baestevel * number; CBND = slice number + 1.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * No action is taken if bit 7 is zero.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "waited %d out of %d tries for drmach_set_lpa on cpu%d",
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni drmach_cpu_ntries - ntries, drmach_cpu_ntries,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni xt_one(cpuid, vtag_flushpage_tl1, (uint64_t)drmach_cpu_sram_va,
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * A detaching CPU is xcalled with an xtrap to drmach_cpu_stop_self() after
03831d35f7499c87d51205817c93e9a8d42c4baestevel * it has been offlined. The function of this routine is to get the cpu
03831d35f7499c87d51205817c93e9a8d42c4baestevel * spinning in a safe place. The requirement is that the system will not
03831d35f7499c87d51205817c93e9a8d42c4baestevel * reference anything on the detaching board (memory and i/o is detached
03831d35f7499c87d51205817c93e9a8d42c4baestevel * elsewhere) and that the CPU not reference anything on any other board
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in the system. This isolation is required during and after the writes
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to the domain masks to remove the board from the domain.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * To accomplish this isolation the following is done:
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 1) Create a locked mapping to the STARDRB data buffer located
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in this cpu's sram. There is one TTE per cpu, initialized in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_cpu_new(). The cpuid is used to select which TTE to use.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Each Safari port pair shares the CPU SRAM on a Serengeti CPU/MEM
03831d35f7499c87d51205817c93e9a8d42c4baestevel * board. The STARDRB buffer is 16KB on Cheetah+ boards, 32KB on Jaguar
03831d35f7499c87d51205817c93e9a8d42c4baestevel * boards. Each STARDRB buffer is logically divided by DR into one
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 8KB page per cpu (or Jaguar core).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 2) Copy the target function (drmach_shutdown_asm) into buffer.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 3) Jump to function now in the cpu sram.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Function will:
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 3.1) Flush its Ecache (displacement).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 3.2) Flush its Dcache with HW mechanism.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 3.3) Flush its Icache with HW mechanism.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 3.4) Flush all valid and _unlocked_ D-TLB and I-TLB entries.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 3.5) Set LPA to NULL
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 3.6) Clear xt_mb to signal completion. Note: cache line is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * recovered by drmach_cpu_poweroff().
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 4) Jump into an infinite loop.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni extern void drmach_shutdown_asm(uint64_t, uint64_t, int, int, uint64_t);
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni extern void drmach_shutdown_asm_end(void);
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni ASSERT(TTE_IS_VALID(tte) && TTE_IS_8K(tte) && TTE_IS_PRIVILEGED(tte) &&
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* copy text. standard bcopy not designed to work in nc space */
03831d35f7499c87d51205817c93e9a8d42c4baestevel *p++ = *q++;
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* zero to assist debug */
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (p < q)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* a parking spot for the stack pointer */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* call copy of drmach_shutdown_asm */
03831d35f7499c87d51205817c93e9a8d42c4baestevel (*(void (*)())drmach_cpu_sram_va)(
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni va_to_pa((void *)&drmach_xt_mb[CPU->cpu_id]));
03831d35f7499c87d51205817c93e9a8d42c4baestevel extern void flush_windows(void);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_PANIC, "CPU %d FAILED TO SHUTDOWN", cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_cpu_status(drmachid_t id, drmach_status_t *stat)
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) strncpy(stat->type, dp->type, sizeof (stat->type));
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_cpu_get_id(drmachid_t id, processorid_t *cpuid)
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (np->n_getprop(np, "implementation#", &impl, sizeof (impl)) == -1) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Flush this cpu's ecache, then ensure all outstanding safari
03831d35f7499c87d51205817c93e9a8d42c4baestevel * transactions have retired.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (p = drmach_bus_sync_list; *p; p++)
03831d35f7499c87d51205817c93e9a8d42c4baestevel (void) ldphys(*p);
03831d35f7499c87d51205817c93e9a8d42c4baestevel *yes = i_ddi_devi_attached(dip) || (state == DDI_DEVSTATE_UP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = ddi_getproplen(DDI_DEV_T_ANY, dip, 0, "device_type", &len);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((rv != DDI_PROP_SUCCESS) || (len > sizeof (dtype)))
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, 0, "device_type",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Get safari portid. All schizo/xmits 0
03831d35f7499c87d51205817c93e9a8d42c4baestevel * safari IDs end in 0x1C.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni rv = ddi_getproplen(DDI_DEV_T_ANY, dip, 0, "portid",
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * All PCI B-Leafs are at configspace 0x70.0000.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Verify if the dip is an instance of MAN 'eri'.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Verify if the parent is schizo(xmits)0 and pci B leaf.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni ((name = ddi_binding_name(parent_dip)) == NULL))
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This RIO could be on XMITS, so get the dip to
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XMITS PCI Leaf.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((parent_dip = ddi_get_parent(parent_dip)) == NULL)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (((name = ddi_binding_name(parent_dip)) == NULL) ||
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Finally make sure it is the MAN eri.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "reg", (caddr_t)®buf, &len) == DDI_PROP_SUCCESS) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The network function of the RIO ASIC will always be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * device 3 and function 1 ("network@3,1").
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_board_find_io_insts(dev_info_t *dip, void *args)
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = ddi_getproplen(DDI_DEV_T_ANY, dip, 0, "portid", &len);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((rv != DDI_PROP_SUCCESS) || (len > sizeof (portid))) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* ignore devices that are not on this board */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((ios->iosram_inst < 0) || (ios->eri_dip == NULL)) {
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni rv = ddi_getproplen(DDI_DEV_T_ANY, dip, 0, "name", &len);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* walk device tree to find iosram instance for the board */
03831d35f7499c87d51205817c93e9a8d42c4baestevel ddi_walk_devs(ddi_get_child(rdip), drmach_board_find_io_insts,
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_io_pre_release: bnum=%d iosram=%d eri=0x%p\n",
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki ios.bnum, ios.iosram_inst, (void *)ios.eri_dip);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Release hold acquired in drmach_board_find_io_insts()
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* call for tunnel switch */
03831d35f7499c87d51205817c93e9a8d42c4baestevel func = (int (*)(dev_info_t *))kobj_getsymvalue("man_dr_attach",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk device tree to find rio dip for the board
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Since we are not interested in iosram instance here,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * initialize it to 0, so that the walk terminates as
03831d35f7499c87d51205817c93e9a8d42c4baestevel * soon as eri dip is found.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Root node doesn't have to be held in any way.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni ddi_walk_devs(dip, drmach_board_find_io_insts,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Release hold acquired in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_board_find_io_insts()
03831d35f7499c87d51205817c93e9a8d42c4baestevel func = (int (*)(dev_info_t *))kobj_getsymvalue("man_dr_detach",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk device tree to find rio dip for the board
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Since we are not interested in iosram instance here,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * initialize it to 0, so that the walk terminates as
03831d35f7499c87d51205817c93e9a8d42c4baestevel * soon as eri dip is found.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Root node doesn't have to be held in any way.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni ddi_walk_devs(dip, drmach_board_find_io_insts,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Release hold acquired in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_board_find_io_insts()
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Always called after drmach_unconfigure() which on Starcat
03831d35f7499c87d51205817c93e9a8d42c4baestevel * unconfigures the branch but doesn't remove it so the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * dip must always exist.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * We held the branch rooted at dip earlier, so at a minimum the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * root i.e. dip must be present in the device tree.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk device tree to find rio dip for the board
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Since we are not interested in iosram instance here,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * initialize it to 0, so that the walk terminates as
03831d35f7499c87d51205817c93e9a8d42c4baestevel * soon as eri dip is found.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Root node doesn't have to be held in any way.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni ddi_walk_devs(dip, drmach_board_find_io_insts, (void *)&ios);
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki DRMACH_PR("drmach_io_post_attach: bnum=%d eri=0x%p\n",
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni (int (*)(dev_info_t *))kobj_getsymvalue("man_dr_attach", 0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Release hold acquired in drmach_board_find_io_insts()
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_io_status(drmachid_t id, drmach_status_t *stat)
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) strncpy(stat->type, dp->type, sizeof (stat->type));
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (chunks-- != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Hardware registers are organized into consecutively
03831d35f7499c87d51205817c93e9a8d42c4baestevel * addressed registers. The reg property's hi and lo fields
03831d35f7499c87d51205817c93e9a8d42c4baestevel * together describe the base address of the register set for
03831d35f7499c87d51205817c93e9a8d42c4baestevel * this memory-controller. Register descriptions and offsets
03831d35f7499c87d51205817c93e9a8d42c4baestevel * (from the base address) are as follows:
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Description Offset Size (bytes)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Timing Control Register I 0x00 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Timing Control Register II 0x08 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Address Decoding Register I 0x10 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Address Decoding Register II 0x18 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Address Decoding Register III 0x20 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Address Decoding Register IV 0x28 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Address Control Register 0x30 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Timing Control Register III 0x38 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Timing Control Register IV 0x40 8
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Memory Timing Control Register V 0x48 8 (Jaguar, Panther only)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * EMU Activity Status Register 0x50 8 (Panther only)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Only the Memory Address Decoding Register and EMU Activity Status
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Register addresses are needed for DRMACH.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_new(drmach_device_t *proto, drmachid_t *idp)
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (count = bank = 0; bank < DRMACH_MC_NBANKS; bank++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If none of the banks had their valid bit set, that means
03831d35f7499c87d51205817c93e9a8d42c4baestevel * post did not configure this MC to participate in the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * domain. So, pretend this node does not exist by returning
03831d35f7499c87d51205817c93e9a8d42c4baestevel * a drmachid of zero.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (count == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* drmach_mem_dispose frees board mem list */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Only one mem unit per board is exposed to the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * PIM layer. The first mem unit encountered during
03831d35f7499c87d51205817c93e9a8d42c4baestevel * tree walk is used to represent all mem units on
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the same board.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* start list of mem units on this board */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * force unum to zero since this is the only mem unit
03831d35f7499c87d51205817c93e9a8d42c4baestevel * that will be visible to the PIM layer.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * board memory size kept in this mem unit only
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* drmach_mem_dispose frees board mem list */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * allow this instance (the first encountered on this board)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to be visible to the PIM layer.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* hide this mem instance behind the first. */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * hide this instance from the caller.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * See drmach_board_find_devices_cb() for details.
03831d35f7499c87d51205817c93e9a8d42c4baestevel } while (mp);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_add_span(drmachid_t id, uint64_t basepa, uint64_t size)
03831d35f7499c87d51205817c93e9a8d42c4baestevel } else if (rv != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* catch this in debug kernels */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_del_span(drmachid_t id, uint64_t basepa, uint64_t size)
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = kcage_range_delete_post_mem_del(basepfn, npages);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (rv != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel "unexpected kcage_range_delete_post_mem_del"
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_get_alignment(drmachid_t id, uint64_t *mask)
03831d35f7499c87d51205817c93e9a8d42c4baestevel static struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel static int len = sizeof (uk2segsz) / sizeof (uk2segsz[0]);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* prime the result with a default value */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* get register value, extract uk and normalize */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* match uk value */
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < len; i++)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * remember largest segment size,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * update mask result
03831d35f7499c87d51205817c93e9a8d42c4baestevel * uk not in table, punt using
03831d35f7499c87d51205817c93e9a8d42c4baestevel * entire slice size. no longer any
03831d35f7499c87d51205817c93e9a8d42c4baestevel * reason to check other banks.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_get_base_physaddr(drmachid_t id, uint64_t *base_addr)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* should not happen, but ... */
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The list is zero terminated.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Offset the pa by a doubleword
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to avoid confusing a pa value of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of zero with the terminator.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_get_memlist(drmachid_t id, struct memlist **ml)
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (chunks-- != 0) {
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni mlist = memlist_add_span(mlist, chunk->mc_base_pa,
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_get_slice_size(drmachid_t id, uint64_t *bytes)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* try to choose a proc on the target board */
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* otherwise, this proc, wherever it is */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_mem_status(drmachid_t id, drmach_status_t *stat)
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* get starting physical address of target memory */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* round down to slice boundary */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* stop at first span that is in slice */
56f33205c9ed776c3c909e07d52e94610a675740Jonathan Adams for (ml = phys_install; ml; ml = ml->ml_next)
56f33205c9ed776c3c909e07d52e94610a675740Jonathan Adams if (ml->ml_address >= pa && ml->ml_address < pa + slice_size)
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) strncpy(stat->type, mp->dev.type, sizeof (stat->type));
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_array_dispose(bp->devices, drmach_device_dispose);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED1*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel } else if (DRMACH_IS_IO_ID(id) && ((drmach_io_t *)id)->scsr_pa != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel uprintf("showlpa %s::%s portid %d, base pa %lx, bound pa %lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* do saf configurator stuff */
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("calling sc_probe_board for bnum=%d\n", bp->bnum);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_pt_ikdeprobe(drmachid_t id, drmach_opts_t *opts)
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_CONT, "DR: in-kernel unprobe board %d\n", bp->bnum);
56f33205c9ed776c3c909e07d52e94610a675740Jonathan Adams for (ml = phys_install; ml; ml = ml->ml_next) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* copy 32 bytes at src_pa to dst_pa */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* increment by 32 bytes */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* decrement by 32 bytes */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_pt_recovercpu(drmachid_t id, drmach_opts_t *opts)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Starcat DR passthrus are for debugging purposes only.
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel sbd_error_t *(*handler)(drmachid_t id, drmach_opts_t *opts);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* the following line must always be last */
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (strncmp(drmach_pt_arr[i].name, opts->copts, len) == 0)
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Since CPU nodes are not configured, it is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * necessary to skip the unconfigure step as
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (; id; ) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_unconfigure() is always called on a configured branch.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * So the root of the branch was held earlier and must exist.
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_unconfigure: unconfiguring DDI branch");
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* The node must have a name */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * NOTE: FORCE flag is no longer needed under devfs
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni char *path = kmem_alloc(MAXPATHLEN, KM_SLEEP);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If non-NULL, fdip is returned held and must be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * released.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If we were unconfiguring an IO board, a call was
03831d35f7499c87d51205817c93e9a8d42c4baestevel * made to man_dr_detach. We now need to call
03831d35f7499c87d51205817c93e9a8d42c4baestevel * man_dr_attach to regain man use of the eri.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni ("man_dr_attach", 0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk device tree to find rio dip for
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the board
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Since we are not interested in iosram
03831d35f7499c87d51205817c93e9a8d42c4baestevel * instance here, initialize it to 0, so
03831d35f7499c87d51205817c93e9a8d42c4baestevel * that the walk terminates as soon as
03831d35f7499c87d51205817c93e9a8d42c4baestevel * eri dip is found.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Root node doesn't have to be held in
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni " eri=0x%p\n",
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni " man_dr_attach\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Release hold acquired in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_board_find_io_insts()
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach interfaces to legacy Starfire platmod logic
03831d35f7499c87d51205817c93e9a8d42c4baestevel * linkage via runtime symbol look up, called from plat_cpu_power*
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Start up a cpu. It is possible that we're attempting to restart
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the cpu after an UNCONFIGURE in which case the cpu will be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * spinning in its cache. So, all we have to do is wakeup him up.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Under normal circumstances the cpu will be coming from a previous
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CONNECT and thus will be spinning in OBP. In both cases, the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * startup sequence is the same.
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_cpu_poweron: starting cpuid %d\n", cp->cpu_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_cpu_poweroff: stopping cpuid %d\n", cp->cpu_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX CHEETAH SUPPORT
03831d35f7499c87d51205817c93e9a8d42c4baestevel * for cheetah, we need to grab the iocage lock since iocage
03831d35f7499c87d51205817c93e9a8d42c4baestevel * memory is used for e$ flush.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Set affinity to ensure consistent reading and writing of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_xt_mb[cpuid] by one "master" CPU directing
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the shutdown of the target CPU.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Capture all CPUs (except for detaching proc) to prevent
03831d35f7499c87d51205817c93e9a8d42c4baestevel * crosscalls to the detaching proc until it has cleared its
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bit in cpu_ready_set.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The CPUs remain paused and the prom_mutex is known to be free.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This prevents blocking when doing prom IEEE-1275 calls at a
03831d35f7499c87d51205817c93e9a8d42c4baestevel * high PIL level.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Quiesce interrupts on the target CPU. We do this by setting
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the CPU 'not ready'- (i.e. removing the CPU from cpu_ready_set) to
03831d35f7499c87d51205817c93e9a8d42c4baestevel * prevent it from receiving cross calls and cross traps.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This prevents the processor from receiving any new soft interrupts.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* setup xt_mb, will be cleared by drmach_shutdown_asm when ready */
03831d35f7499c87d51205817c93e9a8d42c4baestevel xt_one_unchecked(cp->cpu_id, (xcfunc_t *)idle_stop_xcall,
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_xt_mb[cpuid] = 0; /* steal the cache line back */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX CHEETAH SUPPORT
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "drmach_cpu_shutdown_self on cpu%d",
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni drmach_cpu_ntries - ntries, drmach_cpu_ntries, cp->cpu_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Do this here instead of drmach_cpu_shutdown_self() to
03831d35f7499c87d51205817c93e9a8d42c4baestevel * avoid an assertion failure panic in turnstile.c.
03831d35f7499c87d51205817c93e9a8d42c4baestevel CPU_SIGNATURE(OS_SIG, SIGST_DETACHED, SIGSUBST_NULL, cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki extern uint32_t drmach_bc_bzero(void*, size_t);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (rv != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel "iocage scrub failed, drmach_bc_bzero returned %d\n", rv);
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni rv = drmach_bc_bzero(drmach_iocage_vaddr, drmach_iocage_size);
03831d35f7499c87d51205817c93e9a8d42c4baestevel "iocage scrub failed, drmach_bc_bzero rv=%d\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel (((uintptr_t)(x) + (uintptr_t)(a) - 1l) & ~((uintptr_t)(a) - 1l)))
03831d35f7499c87d51205817c93e9a8d42c4baestevel * HPOST wants the address of the cage to be 64 megabyte-aligned
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and in megabyte units.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The size of the cage is also in megabyte units.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ASSERT(drmach_iocage_paddr == ALIGN(drmach_iocage_paddr, 0x4000000));
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_iocage_paddr_mbytes = drmach_iocage_paddr / 0x100000;
03831d35f7499c87d51205817c93e9a8d42c4baestevel tbrq->memaddrhi = (uint32_t)(drmach_iocage_paddr_mbytes >> 32);
03831d35f7499c87d51205817c93e9a8d42c4baestevel tbrq->memaddrlo = (uint32_t)drmach_iocage_paddr_mbytes;
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_iocage_mem_get: hi: 0x%x", tbrq->memaddrhi);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_iocage_mem_get: lo: 0x%x", tbrq->memaddrlo);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_iocage_mem_get: size: 0x%x", tbrq->memlen);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_iocage_cpu_acquire(drmach_device_t *dp, cpu_flag_t *oflags)
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: attempting to acquire CPU id %d", fn, cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: cpu_get(%d) returned NULL", fn, cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: skipping offlined CPU id %d", fn, cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * There is a known HW bug where a Jaguar CPU in Safari port 0 (SBX/P0)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * can fail to receive an XIR. To workaround this issue until a hardware
03831d35f7499c87d51205817c93e9a8d42c4baestevel * fix is implemented, we will exclude the selection of these CPUs.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Once a fix is implemented in hardware, this code should be updated
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to allow Jaguar CPUs that have the fix to be used. However, support
03831d35f7499c87d51205817c93e9a8d42c4baestevel * must be retained to skip revisions that do not have this fix.
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: error getting impl. of CPU id %d", fn, cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (IS_JAGUAR(impl) && (STARCAT_CPUID_TO_LPORT(cpuid) == 0) &&
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: excluding CPU id %d: port 0 on jaguar",
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: cpu_offline failed for CPU id %d", fn, cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: cpu_poweroff failed for CPU id %d", fn, cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: cpu_unconfigure failed for CPU id %d", fn,
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel "during I/O cage test selection",
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Attempt to acquire all the CPU devices passed in. It is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * assumed that all the devices in the list are the cores of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * a single CMP device. Non CMP devices can be handled as a
03831d35f7499c87d51205817c93e9a8d42c4baestevel * single core CMP by passing in a one element list.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Success is only returned if *all* the devices in the list
03831d35f7499c87d51205817c93e9a8d42c4baestevel * can be acquired. In the failure case, none of the devices
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in the list will be held as acquired.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_iocage_cmp_acquire(drmach_device_t **dpp, cpu_flag_t *oflags)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk the list of CPU devices (cores of a CMP)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and attempt to acquire them. Bail out if an
03831d35f7499c87d51205817c93e9a8d42c4baestevel * error is encountered.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* check for the end of the list */
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_iocage_cpu_acquire(dpp[curr], &oflags[curr]);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (rv != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check for an error.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (rv != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Make a best effort attempt to return any cores
03831d35f7499c87d51205817c93e9a8d42c4baestevel * that were already acquired before the error was
03831d35f7499c87d51205817c93e9a8d42c4baestevel * encountered.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < curr; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_iocage_cpu_return(drmach_device_t *dp, cpu_flag_t oflags)
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("%s: attempting to return CPU id: %d", fn, cpuid);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The component was never set to unconfigured during the IO
03831d35f7499c87d51205817c93e9a8d42c4baestevel * cage test, so we need to leave marked as busy to prevent
03831d35f7499c87d51205817c93e9a8d42c4baestevel * further DR operations involving this component.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_WARN, "cpu_get failed on CPU id %d after "
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * drmach_iocage_cpu_acquire will accept cpus in state P_ONLINE or
03831d35f7499c87d51205817c93e9a8d42c4baestevel * P_NOINTR. Need to return to previous user-visible state.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_iocage_cpu_get(dr_testboard_req_t *tbrq, drmach_device_t **dpp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk the board list.
03831d35f7499c87d51205817c93e9a8d42c4baestevel b_rv = drmach_array_first(drmach_boards, &b_idx, &b_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (b_rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel b_rv = drmach_array_next(drmach_boards, &b_idx, &b_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* An AXQ restriction disqualifies MCPU's as candidates. */
03831d35f7499c87d51205817c93e9a8d42c4baestevel b_rv = drmach_array_next(drmach_boards, &b_idx, &b_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Walk the device list of this board.
03831d35f7499c87d51205817c93e9a8d42c4baestevel d_rv = drmach_array_first(bp->devices, &d_idx, &d_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (d_rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* only interested in CPU devices */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The following code assumes two properties
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of a CMP device:
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 1. All cores of a CMP are grouped together
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in the device list.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 2. There will only be a maximum of two cores
03831d35f7499c87d51205817c93e9a8d42c4baestevel * present in the CMP.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If either of these two properties change,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * this code will have to be revisited.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Get the next device. It may or may not be used.
03831d35f7499c87d51205817c93e9a8d42c4baestevel d_rv = drmach_array_next(bp->devices, &d_idx, &d_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The second device is only interesting for
03831d35f7499c87d51205817c93e9a8d42c4baestevel * this pass if it has the same portid as the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * first device. This implies that both are
03831d35f7499c87d51205817c93e9a8d42c4baestevel * cores of the same CMP.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Attempt to acquire all cores of the CMP.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check if the search for the second core was
03831d35f7499c87d51205817c93e9a8d42c4baestevel * successful. If not, the next iteration should
03831d35f7499c87d51205817c93e9a8d42c4baestevel * use that device.
03831d35f7499c87d51205817c93e9a8d42c4baestevel d_rv = drmach_array_next(bp->devices, &d_idx, &d_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel b_rv = drmach_array_next(drmach_boards, &b_idx, &b_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (drerr_new(1, ESTC_IOCAGE_NO_CPU_AVAIL, NULL));
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Setup an iocage by acquiring a cpu and memory.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_iocage_setup(dr_testboard_req_t *tbrq, drmach_device_t **dpp,
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef enum {
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Table of saved state for paused slot1 devices.
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic drmach_slot1_pause_t *drmach_slot1_paused[STARCAT_BDSET_MAX];
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif /* DEBUG */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_is_slot1_pause_axq(dev_info_t *dip, char *name, int *id, uint64_t *reg)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < STARCAT_SLOT1_CPU_MAX; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* maxcat cpu present */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
03831d35f7499c87d51205817c93e9a8d42c4baestevel "reg", (caddr_t)regs, ®len) != DDI_PROP_SUCCESS) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_is_slot1_pause_axq: no reg prop for "
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Allocate an entry in the slot1_paused state table.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_slot1_pause_add_axq(dev_info_t *axq_dip, char *axq_name, int axq_portid,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX This dip should really be held (via ndi_hold_devi())
03831d35f7499c87d51205817c93e9a8d42c4baestevel * before saving it in the axq pause structure. However that
03831d35f7499c87d51205817c93e9a8d42c4baestevel * would prevent DR as the pause data structures persist until
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the next suspend. drmach code should be modified to free the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the slot 1 pause data structures for a boardset when its
03831d35f7499c87d51205817c93e9a8d42c4baestevel * slot 1 board is DRed out. The dip can then be released via
03831d35f7499c87d51205817c93e9a8d42c4baestevel * ndi_rele_devi() when the pause data structure is freed
03831d35f7499c87d51205817c93e9a8d42c4baestevel * allowing DR to proceed. Until this change is made, drmach
03831d35f7499c87d51205817c93e9a8d42c4baestevel * code should be careful about dereferencing the saved dip
03831d35f7499c87d51205817c93e9a8d42c4baestevel * as it may no longer exist.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < DRMACH_S1P_SAMPLE_MAX; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_slot1_pause_free(drmach_slot1_pause_t **slot1_paused)
03831d35f7499c87d51205817c93e9a8d42c4baestevel int i, j, k;
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < STARCAT_BDSET_MAX; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (j = 0; j < STARCAT_SLOT1_IO_MAX; j++)
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (k = 0; k < DRMACH_SCHIZO_PCI_LEAF_MAX; k++)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Tree walk callback routine. If dip represents a Schizo PCI leaf,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * fill in the appropriate info in the slot1_paused state table.
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_slot1_pause_t **slot1_paused = (drmach_slot1_pause_t **)arg;
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
03831d35f7499c87d51205817c93e9a8d42c4baestevel "name", (caddr_t)buf, &buflen) != DDI_PROP_SUCCESS ||
03831d35f7499c87d51205817c93e9a8d42c4baestevel strncmp(buf, DRMACH_PCI_NAMEPROP, strlen(DRMACH_PCI_NAMEPROP))) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
03831d35f7499c87d51205817c93e9a8d42c4baestevel "reg", (caddr_t)regs, ®len) != DDI_PROP_SUCCESS) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_find_slot1_io: no reg prop for pci "
03831d35f7499c87d51205817c93e9a8d42c4baestevel ASSERT(leaf_offset == 0x600000 || leaf_offset == 0x700000);
03831d35f7499c87d51205817c93e9a8d42c4baestevel ASSERT(slot1_paused[exp]->schizo[ioc_unum].csr_basepa == 0x0UL ||
03831d35f7499c87d51205817c93e9a8d42c4baestevel slot1_paused[exp]->schizo[ioc_unum].csr_basepa == schizo_csr_pa);
03831d35f7499c87d51205817c93e9a8d42c4baestevel slot1_paused[exp]->schizo[ioc_unum].csr_basepa = schizo_csr_pa;
03831d35f7499c87d51205817c93e9a8d42c4baestevel pci = &slot1_paused[exp]->schizo[ioc_unum].pci[leaf_unum];
03831d35f7499c87d51205817c93e9a8d42c4baestevel * XXX This dip should really be held (via ndi_hold_devi())
03831d35f7499c87d51205817c93e9a8d42c4baestevel * before saving it in the pci pause structure. However that
03831d35f7499c87d51205817c93e9a8d42c4baestevel * would prevent DR as the pause data structures persist until
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the next suspend. drmach code should be modified to free the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the slot 1 pause data structures for a boardset when its
03831d35f7499c87d51205817c93e9a8d42c4baestevel * slot 1 board is DRed out. The dip can then be released via
03831d35f7499c87d51205817c93e9a8d42c4baestevel * ndi_rele_devi() when the pause data structure is freed
03831d35f7499c87d51205817c93e9a8d42c4baestevel * allowing DR to proceed. Until this change is made, drmach
03831d35f7499c87d51205817c93e9a8d42c4baestevel * code should be careful about dereferencing the saved dip as
03831d35f7499c87d51205817c93e9a8d42c4baestevel * it may no longer exist.
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_find_slot1_io: name=%s, portid=0x%x, dip=%p\n",
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_slot1_pause_add_io(drmach_slot1_pause_t **slot1_paused)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Root node doesn't have to be held
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Save the interrupt mapping registers for each non-idle interrupt
03831d35f7499c87d51205817c93e9a8d42c4baestevel * represented by the bit pairs in the saved interrupt state
03831d35f7499c87d51205817c93e9a8d42c4baestevel * diagnostic registers for this PCI leaf.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_s1p_intr_map_reg_save(drmach_s1p_pci_t *pci, drmach_sr_iter_t iter)
03831d35f7499c87d51205817c93e9a8d42c4baestevel Xmits = (strcmp(dname, XMITS_BINDING_NAME) == 0) ? 1 : 0;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 1st pass allocates, 2nd pass populates.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < 2; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * PCI slot interrupts
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Xmits Interrupt Number Offset(ino) Assignments
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 00-17 PCI Slot Interrupts
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 18-1f Not Used
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Xmits Interrupt Number Offset(ino) Assignments
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 20-2f Not Used
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 30-37 Internal interrupts
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 38-3e Not Used
03831d35f7499c87d51205817c93e9a8d42c4baestevel * OBIO and internal schizo interrupts
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Each PCI leaf has a set of mapping registers for all
03831d35f7499c87d51205817c93e9a8d42c4baestevel * possible interrupt sources except the NewLink interrupts.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_s1p_axq_update(drmach_s1p_axq_t *axq, drmach_sr_iter_t iter)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Select l2_io_queue counter by writing L2_IO_Q mux
03831d35f7499c87d51205817c93e9a8d42c4baestevel * input to bits 0-6 of perf cntr select reg.
03831d35f7499c87d51205817c93e9a8d42c4baestevel stphysio(axq->reg_basepa + AXQ_SLOT1_PERFCNT_SEL, reg);
03831d35f7499c87d51205817c93e9a8d42c4baestevel axq->pic_l2_io_q[iter] = ldphysio(axq->reg_basepa + AXQ_SLOT1_PERFCNT0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_s1p_axq_update: axq #%d pic_l2_io_q[%d]=%d\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel ddi_get_instance(axq->dip), iter, axq->pic_l2_io_q[iter]);
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_s1p_schizo_update(drmach_s1p_schizo_t *schizo, drmach_sr_iter_t iter)
03831d35f7499c87d51205817c93e9a8d42c4baestevel lddphysio(schizo->csr_basepa + SCHIZO_CB_CSR_OFFSET);
03831d35f7499c87d51205817c93e9a8d42c4baestevel lddphysio(schizo->csr_basepa + SCHIZO_CB_ERRCTRL_OFFSET);
03831d35f7499c87d51205817c93e9a8d42c4baestevel lddphysio(schizo->csr_basepa + SCHIZO_CB_ERRLOG_OFFSET);
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < DRMACH_SCHIZO_PCI_LEAF_MAX; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Called post-suspend and pre-resume to snapshot the suspend state
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of slot1 AXQs and Schizos.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_slot1_pause_update(drmach_slot1_pause_t **slot1_paused,
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < STARCAT_BDSET_MAX; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (j = 0; j < STARCAT_SLOT1_IO_MAX; j++)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Starcat hPCI Schizo devices.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The name field is overloaded. NULL means the slot (interrupt concentrator
03831d35f7499c87d51205817c93e9a8d42c4baestevel * bus) is not used. intr_mask is a bit mask representing the 4 possible
03831d35f7499c87d51205817c93e9a8d42c4baestevel * interrupts per slot, on if valid (rio does not use interrupt lines 0, 1).
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel} drmach_schz_slot_intr[][DRMACH_SCHIZO_PCI_LEAF_MAX] = {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * See Schizo Specification, Revision 51 (May 23, 2001), Section 22.4.4
03831d35f7499c87d51205817c93e9a8d42c4baestevel * "Interrupt Registers", Table 22-69, page 306.
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic char *
03831d35f7499c87d51205817c93e9a8d42c4baestevel default: return ("Reserved");
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_s1p_decode_slot_intr(int exp, int unum, drmach_s1p_pci_t *pci,
03831d35f7499c87d51205817c93e9a8d42c4baestevel (COMMON_CLEAR_INTR_REG_MASK << DRMACH_INTR_MASK_SHIFT(ino))) !=
03831d35f7499c87d51205817c93e9a8d42c4baestevel slot_devname = drmach_schz_slot_intr[slot][unum].name;
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) snprintf(namebuf, sizeof (namebuf), "slot %d (INVALID)",
03831d35f7499c87d51205817c93e9a8d42c4baestevel intr_mask = drmach_schz_slot_intr[slot][unum].intr_mask;
03831d35f7499c87d51205817c93e9a8d42c4baestevel prom_printf("IO%d/P%d PCI slot interrupt: ino=0x%x, source device=%s, "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "interrupt line=%d%s\n", exp, unum, ino, slot_devname, intr_line,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Log interrupt source device info for all valid, pending interrupts
03831d35f7499c87d51205817c93e9a8d42c4baestevel * on each Schizo PCI leaf. Called if Schizo has logged a Safari bus
03831d35f7499c87d51205817c93e9a8d42c4baestevel * error in the error ctrl reg.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_s1p_schizo_log_intr(drmach_s1p_schizo_t *schizo, int exp,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check the saved interrupt mapping registers. If interrupt is valid,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * map the ino to the Schizo source device and check that the pci
03831d35f7499c87d51205817c93e9a8d42c4baestevel * slot and interrupt line are valid.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < DRMACH_SCHIZO_PCI_LEAF_MAX; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * PCI slot interrupt
03831d35f7499c87d51205817c93e9a8d42c4baestevel * OBIO interrupt
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Internal interrupt
03831d35f7499c87d51205817c93e9a8d42c4baestevel "interrupt: ino=0x%x (%s)\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * NewLink interrupt
03831d35f7499c87d51205817c93e9a8d42c4baestevel "exp=%d, schizo=%d, pci_leaf=%c, "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "ino=0x%x, intr_map_reg=0x%lx\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * See Schizo Specification, Revision 51 (May 23, 2001), Section 22.2.4
03831d35f7499c87d51205817c93e9a8d42c4baestevel * "Safari Error Control/Log Registers", Table 22-11, page 248.
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_SCHIZO_SAFARI_UNMAPPED_ERR (0x1ull << 4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check for possible error indicators prior to resuming the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * AXQ driver, which will de-assert slot1 AXQ_DOMCTRL_PAUSE.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_slot1_pause_verify(drmach_slot1_pause_t **slot1_paused,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check for logged schizo bus error and pending interrupts.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < STARCAT_BDSET_MAX; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (j = 0; j < STARCAT_SLOT1_IO_MAX; j++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel "attempt detected during "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "copy-rename (%s):\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check for changes in axq l2_io_q performance counters (2nd pass only)
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < STARCAT_BDSET_MAX; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel "detected on IO%d during copy-rename: "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "AXQ l2_io_q performance counter "
03831d35f7499c87d51205817c93e9a8d42c4baestevel "start=%d, end=%d\n", i,
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_sr_insert(struct drmach_sr_list **lp, dev_info_t *dip)
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki DRMACH_PR("drmach_sr_insert: adding dip %p\n", (void *)dip);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* establish list */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* place new node behind head node on ring list */
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_sr_delete(struct drmach_sr_list **lp, dev_info_t *dip)
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki DRMACH_PR("drmach_sr_delete: searching for dip %p\n", (void *)dip);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* start search with mostly likely node */
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki " disposed sr node for dip %p",
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* every dip should be found during resume */
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki DRMACH_PR("ERROR: drmach_sr_delete: can't find dip %p", (void *)dip);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* schedule init for next suspend */
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni DDI_PROP_DONTPASS, "name", (caddr_t)name, &len);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel drmach_is_slot1_pause_axq(dip, name, &portid, ®)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (strncmp(op->name, name, strlen(op->name)) == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The ordering array declares the strict sequence in which
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the named drivers are to suspended. Each element in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the array may have a double-linked ring list of driver
03831d35f7499c87d51205817c93e9a8d42c4baestevel * instances (dip) in the order in which they were presented
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to drmach_verify_sr. If present, walk the list in the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * forward direction to suspend each instance.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni (sizeof (drmach_sr_ordered) / sizeof (drmach_sr_ordered[0]));
03831d35f7499c87d51205817c93e9a8d42c4baestevel * walk ordering array and rings backwards to resume dips
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in reverse order in which they were suspended
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Log a DR sysevent.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return value: 0 success, non-zero failure.
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_log_sysevent(int board, char *hint, int flag, int verbose)
03831d35f7499c87d51205817c93e9a8d42c4baestevel km_flag = (flag == SE_SLEEP) ? KM_SLEEP : KM_NOSLEEP;
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (drmach_board_name(board, attach_pnt, MAXNAMELEN)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel DRMACH_PR("drmach_log_sysevent: %s %s, flag: %d, verbose: %d\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((ev = sysevent_alloc(EC_DR, ESC_DR_AP_STATE_CHANGE,
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((rv = sysevent_add_attr(&evnt_attr_list, DR_AP_ID,
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((rv = sysevent_add_attr(&evnt_attr_list, DR_HINT,
03831d35f7499c87d51205817c93e9a8d42c4baestevel (void) sysevent_attach_attributes(ev, evnt_attr_list);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Log the event but do not sleep waiting for its
03831d35f7499c87d51205817c93e9a8d42c4baestevel * delivery. This provides insulation from syseventd.
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni "drmach_log_sysevent failed (rv %d) for %s %s\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Initialize the mem_slice portion of a claim/unconfig/unclaim mailbox message.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Only the valid entries are modified, so the array should be zeroed out
03831d35f7499c87d51205817c93e9a8d42c4baestevel * initially.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < AXQ_MAX_EXP; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (c & 0x20) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Initialize the mem_regs portion of a claim/unconfig/unclaim mailbox message.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Only the valid entries are modified, so the array should be zeroed out
03831d35f7499c87d51205817c93e9a8d42c4baestevel * initially.
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* CONSTCOND */
03831d35f7499c87d51205817c93e9a8d42c4baestevel ASSERT(DRMACH_MC_NBANKS == (PMBANKS_PER_PORT * LMBANKS_PER_PMBANK));
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Do not allow physical address range modification if either board on this
03831d35f7499c87d51205817c93e9a8d42c4baestevel * expander has processors in NULL LPA mode (CBASE=CBND=NULL).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * A side effect of NULL proc LPA mode in Starcat SSM is that local reads will
03831d35f7499c87d51205817c93e9a8d42c4baestevel * install the cache line as owned/dirty as a result of the RTSR transaction.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * See section 5.2.3 of the Safari spec. All processors will read the bus sync
03831d35f7499c87d51205817c93e9a8d42c4baestevel * list before the rename after flushing local caches. When copy-rename
03831d35f7499c87d51205817c93e9a8d42c4baestevel * requires changing the physical address ranges (i.e. smaller memory target),
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the bus sync list contains physical addresses that will not exist after the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * rename. If these cache lines are owned due to a RTSR, a system error can
03831d35f7499c87d51205817c93e9a8d42c4baestevel * occur following the rename when these cache lines are evicted and a writeback
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is attempted.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Incoming parameter represents either the copy-rename source or a candidate
03831d35f7499c87d51205817c93e9a8d42c4baestevel * target memory board. On Starcat, only slot0 boards may have memory.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This is reason enough to fail the request, no need
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to check the device list for cpus.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Check for MCPU board on the same expander.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The board flag DRMACH_NULL_PROC_LPA can be set for all board
03831d35f7499c87d51205817c93e9a8d42c4baestevel * types, as it is derived at from the POST gdcd board flag
03831d35f7499c87d51205817c93e9a8d42c4baestevel * L1SSFLG_THIS_L1_NULL_PROC_LPA, which can be set (and should be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * ignored) for boards with no processors. Since NULL proc LPA
03831d35f7499c87d51205817c93e9a8d42c4baestevel * applies only to processors, we walk the devices array to detect
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_array_get(drmach_boards, s0bp->bnum + 1, &s1id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = drmach_array_first(s1bp->devices, &d_idx, &d_id);
03831d35f7499c87d51205817c93e9a8d42c4baestevel while (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Fail MCPU in NULL LPA mode.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (1);