Searched defs:reg (Results 76 - 100 of 125) sorted by relevance

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/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/ath/ath9k/
H A Dath9k_ar9003_phy.c609 u32 reg = INI_RA(iniArr, i, 0); local
612 REG_WRITE(ah, reg, val);
H A Dath9k_ar9003_eeprom.c3579 unsigned long reg; local
3586 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3587 reg &= ~0x00ffffc0;
3588 reg |= 0x5 << 21;
3589 reg |= 0x5 << 18;
3590 reg |= 0x5 << 15;
3591 reg |= 0x5 << 12;
3592 reg |= 0x5 << 9;
3593 reg |= 0x5 << 6;
3594 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
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H A Dath9k_hw.c93 int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) argument
98 if ((REG_READ(ah, reg) & mask) == val)
105 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
106 timeout, reg, REG_READ(ah, reg), mask, val);
460 * read the reg when chip is asleep.
867 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) argument
869 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1192 u32 reg; local
1198 reg
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/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/
H A Dbnx2.c159 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) argument
174 val1 = (bp->phy_addr << 21) | (reg << 16) |
216 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) argument
231 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
728 u32 reg; local
736 bnx2_read_phy(bp, MII_BMCR, &reg);
737 if (!(reg & BMCR_RESET)) {
2123 u32 reg; local
2176 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
2177 if (reg
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H A Dforcedeth.c93 u32 reg; local
98 reg = readl ( ioaddr + NvRegMIIControl );
99 if ( reg & NVREG_MIICTL_INUSE ) {
104 reg = ( addr << NVREG_MIICTL_ADDRSHIFT ) | miireg;
107 reg |= NVREG_MIICTL_WRITE;
109 writel ( reg, ioaddr + NvRegMIIControl );
113 DBG ( "mii_rw of reg %d at PHY %d timed out.\n",
118 DBG ( "mii_rw wrote 0x%x to reg %d at PHY %d\n",
122 DBG ( "mii_rw of reg %d at PHY %d failed.\n",
127 DBG ( "mii_rw read from reg
1227 u32 mii_control, mii_control_1000, reg; local
1731 int reg; local
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H A Dnatsemi.h265 unsigned int reg; member in struct:natsemi_ring
273 * @v reg Descriptor start address register
277 unsigned int reg ) {
279 ring->reg = reg;
H A Dprism2.c184 static inline UINT16 hfa384x_getreg( hfa384x_t *hw, UINT reg )
187 return inw ( hw->iobase + reg );
189 return readw ( hw->membase + reg );
194 static inline void hfa384x_setreg( hfa384x_t *hw, UINT16 val, UINT reg )
197 outw ( val, hw->iobase + reg );
199 writew ( val, hw->membase + reg );
208 static inline UINT16 hfa384x_getreg_noswap( hfa384x_t *hw, UINT reg )
210 return hfa384x_getreg ( hw, reg );
212 static inline void hfa384x_setreg_noswap( hfa384x_t *hw, UINT16 val, UINT reg )
214 hfa384x_setreg ( hw, val, reg );
241 UINT16 reg = 0; local
304 UINT16 reg; local
351 UINT16 reg = 0; local
590 UINT16 reg; local
612 UINT16 reg; local
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H A Drealtek.h178 #define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) )
222 unsigned int reg; member in struct:realtek_ring
232 * @v reg Descriptor start address register
236 unsigned int reg ) {
238 ring->reg = reg;
H A Dsis190.c99 static void mdio_write(void *ioaddr, int phy_id, int reg, int val) argument
102 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
106 static int mdio_read(void *ioaddr, int phy_id, int reg) argument
109 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
114 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val) argument
118 mdio_write(tp->mmio_addr, phy_id, reg, val);
121 static int __mdio_read(struct net_device *dev, int phy_id, int reg) argument
125 return mdio_read(tp->mmio_addr, phy_id, reg);
128 static u16 mdio_read_latched(void *ioaddr, int phy_id, int reg) argument
130 mdio_read(ioaddr, phy_id, reg);
134 sis190_read_eeprom(void *ioaddr, u32 reg) argument
789 u16 reg[2][2] = { local
917 sis190_set_rgmii(struct sis190_private *tp, u8 reg) argument
967 u8 reg, tmp8; local
1054 u8 reg; local
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H A Dskge.c62 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
63 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
428 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) argument
432 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
451 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) argument
454 if (__xm_phy_read(hw, port, reg, &v))
460 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) argument
464 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
513 u32 reg; local
531 reg
632 u16 reg; member in struct:__anon15213
1028 u32 reg = skge_read32(hw, B2_GP_IO); local
1161 gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) argument
1181 __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) argument
1201 gm_phy_read(struct skge_hw *hw, int port, u16 reg) argument
1315 u32 reg; local
1332 u32 reg; local
1530 u16 reg; local
2135 u32 reg; local
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H A Dtlan.c1095 * reg The register whose contents are to be
1107 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val) argument
1128 TLan_MiiSendData(BASE, reg, 5); /* Register # */
1250 * reg The register whose contents are to be
1261 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val) argument
1278 TLan_MiiSendData(BASE, reg, 5); /* Register # */
H A Dsky2.c130 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) argument
136 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) argument
162 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
184 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) argument
187 __gm_phy_read(hw, port, reg, &v);
211 u32 reg; local
215 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
217 reg &= P_ASPM_CONTROL_MSK;
218 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
256 u16 reg; local
299 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; local
684 u16 reg; local
1412 u16 reg; local
1443 u16 reg; local
2157 u16 reg; local
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/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c85 int tg3_readphy(struct tg3 *tp, int reg, u32 *val) argument
102 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
221 int tg3_writephy(struct tg3 *tp, int reg, u32 val) argument
229 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
240 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
410 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) argument
415 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
422 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) argument
425 if (reg
547 tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) argument
574 u32 reg = MII_TG3_FET_SHDW_MISCCTRL; local
1216 u32 reg; local
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/vbox/src/VBox/ExtPacks/VBoxDTrace/onnv/uts/intel/dtrace/
H A Dfasttrap_isa.c73 #define FASTTRAP_MODRM(mod, reg, rm) (((mod) << 6) | ((reg) << 3) | (rm))
367 uint_t reg = FASTTRAP_MODRM_REG(instr[start + 1]); local
370 if (reg == 2 || reg == 4) {
373 if (reg == 2)
566 uint_t reg = FASTTRAP_MODRM_REG(instr[rmindex]); local
575 * the reg field may determine the op code
581 if (reg != 0) {
595 FASTTRAP_MODRM(2, reg, r
1498 greg_t *reg; local
1703 fasttrap_getreg(struct regs *rp, uint_t reg) argument
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/vbox/src/VBox/Devices/Bus/
H A DDevPCI.cpp367 int reg; local
370 reg = PCI_ROM_SLOT;
372 reg = (address - 0x10) >> 2;
374 r = &d->Int.s.aIORegions[reg];
378 if (reg == PCI_ROM_SLOT) {
/vbox/src/VBox/Devices/Graphics/shaderlib/
H A Dshader.c191 e->register_idx = s->reg.reg.idx;
192 e->mask = s->reg.write_mask;
338 const struct wined3d_shader_register *reg, enum wined3d_shader_type shader_type)
340 switch (reg->type)
343 if (shader_type == WINED3D_SHADER_TYPE_PIXEL) reg_maps->texcoord |= 1 << reg->idx;
344 else reg_maps->address |= 1 << reg->idx;
348 reg_maps->temporary |= 1 << reg->idx;
354 if (reg->rel_addr)
367 ((IWineD3DPixelShaderImpl *)shader)->input_reg_used[reg
337 shader_record_register_usage(IWineD3DBaseShaderImpl *shader, struct shader_reg_maps *reg_maps, const struct wined3d_shader_register *reg, enum wined3d_shader_type shader_type) argument
867 shader_dump_register(const struct wined3d_shader_register *reg, const struct wined3d_shader_version *shader_version) argument
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/vbox/src/VBox/Devices/PC/ipxe/src/drivers/infiniband/
H A Dlinda.c1830 * @v reg Register
1837 unsigned int reg, unsigned int value,
1853 location = LINDA_EPB_LOC ( cs, channel, element, reg );
1867 linda, cs, channel, element, reg, old_value, value );
2006 unsigned int reg; local
2012 reg = LINDA_EPB_ADDRESS_REG ( param->address );
2023 channel, element, reg,
1835 linda_ib_epb_mod_reg( struct linda *linda, unsigned int cs, unsigned int channel, unsigned int element, unsigned int reg, unsigned int value, unsigned int mask ) argument
H A Dqib7322.c2159 * @v reg AHB register
2164 static int qib7322_ahb_mod_reg_all ( struct qib7322 *qib7322, unsigned int reg, argument
2173 location = QIB7322_AHB_LOCATION ( port, channel, reg );
/vbox/src/VBox/Devices/PC/ipxe/src/drivers/net/ath/ath5k/
H A Dath5k_phy.c33 #include "reg.h"
1762 * on a specific reg domain.
1764 * TODO: Map our current reg domain to one of the 3 available
1765 * reg domain ids so that we can support more CTLs. */
2129 u32 reg; local
2135 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2136 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2149 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2153 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2156 reg |
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/vbox/src/VBox/Additions/WINNT/Graphics/Wine/wined3d/
H A Dshader.c191 e->register_idx = s->reg.reg.idx;
192 e->mask = s->reg.write_mask;
338 const struct wined3d_shader_register *reg, enum wined3d_shader_type shader_type)
340 switch (reg->type)
343 if (shader_type == WINED3D_SHADER_TYPE_PIXEL) reg_maps->texcoord |= 1 << reg->idx;
344 else reg_maps->address |= 1 << reg->idx;
348 reg_maps->temporary |= 1 << reg->idx;
354 if (reg->rel_addr)
367 ((IWineD3DPixelShaderImpl *)shader)->input_reg_used[reg
337 shader_record_register_usage(IWineD3DBaseShaderImpl *shader, struct shader_reg_maps *reg_maps, const struct wined3d_shader_register *reg, enum wined3d_shader_type shader_type) argument
867 shader_dump_register(const struct wined3d_shader_register *reg, const struct wined3d_shader_version *shader_version) argument
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/vbox/src/VBox/Additions/WINNT/Graphics/Wine_new/wined3d/
H A Dshader.c222 e->register_idx = s->reg.reg.idx[0].offset;
223 e->mask = s->reg.write_mask;
394 const struct wined3d_shader_register *reg, enum wined3d_shader_type shader_type)
396 switch (reg->type)
400 reg_maps->texcoord |= 1 << reg->idx[0].offset;
402 reg_maps->address |= 1 << reg->idx[0].offset;
406 reg_maps->temporary |= 1 << reg->idx[0].offset;
412 if (reg->idx[0].rel_addr)
425 shader->u.ps.input_reg_used[reg
393 shader_record_register_usage(struct wined3d_shader *shader, struct wined3d_shader_reg_maps *reg_maps, const struct wined3d_shader_register *reg, enum wined3d_shader_type shader_type) argument
572 struct wined3d_shader_register *reg = &ins.declaration.src.reg; local
837 struct wined3d_shader_register reg = ins.src[i].reg; local
966 shader_dump_register(const struct wined3d_shader_register *reg, const struct wined3d_shader_version *shader_version) argument
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H A Dshader_sm4.c337 static void map_sysval(enum wined3d_sysval_semantic sysval, struct wined3d_shader_register *reg) argument
345 reg->type = sysval_map[i].register_type;
346 reg->idx[0].offset = sysval_map[i].register_idx;
351 static void map_register(const struct wined3d_sm4_data *priv, struct wined3d_shader_register *reg) argument
356 if (reg->type == WINED3DSPR_OUTPUT)
369 if (s->elements[i].register_idx == reg->idx[0].offset)
371 map_sysval(s->elements[i].sysval_semantic, reg);
630 if (!shader_sm4_read_param(priv, ptr, data_type, &src_param->reg, &src_param->modifiers))
636 if (src_param->reg.type == WINED3DSPR_IMMCONST)
671 if (!shader_sm4_read_param(priv, ptr, data_type, &dst_param->reg,
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/vbox/src/recompiler/target-i386/
H A Dops_sse.h1834 static inline int pcmp_elen(int reg, uint32_t ctrl) argument
1840 val = abs1((int64_t) env->regs[reg]);
1842 val = abs1((int32_t) env->regs[reg]);
/vbox/src/recompiler/tcg/i386/
H A Dtcg-target.c623 static inline void tcg_out_push(TCGContext *s, int reg) argument
625 tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0);
628 static inline void tcg_out_pop(TCGContext *s, int reg) argument
630 tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0);
647 static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) argument
654 tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg);
656 tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg);
661 static inline void tcg_out_bswap32(TCGContext *s, int reg) argument
666 tcg_out_rolw_8(TCGContext *s, int reg) argument
708 tcg_out_bswap64(TCGContext *s, int reg) argument
774 tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) argument
785 tcg_out_subi(TCGContext *s, int reg, tcg_target_long val) argument
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/vbox/src/recompiler/tcg/
H A Dtcg.c271 void tcg_set_frame(TCGContext *s, int reg, argument
276 s->frame_reg = reg;
300 static inline int tcg_global_reg_new_internal(TCGType type, int reg, argument
311 if (tcg_regset_test_reg(s->reserved_regs, reg))
319 ts->reg = reg;
322 tcg_regset_set_reg(s->reserved_regs, reg);
326 TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name) argument
330 idx = tcg_global_reg_new_internal(TCG_TYPE_I32, reg, name);
334 TCGv_i64 tcg_global_reg_new_i64(int reg, cons argument
342 tcg_global_mem_new_internal(TCGType type, int reg, tcg_target_long offset, const char *name) argument
403 tcg_global_mem_new_i32(int reg, tcg_target_long offset, const char *name) argument
412 tcg_global_mem_new_i64(int reg, tcg_target_long offset, const char *name) argument
1398 int reg, k; local
1448 tcg_reg_free(TCGContext *s, int reg) argument
1470 int i, reg; local
1499 int reg; local
1589 int reg; local
1649 int i, k, nb_iargs, nb_oargs, reg; local
1814 int nb_iargs, nb_oargs, flags, nb_regs, i, reg, nb_params; local
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