a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * iPXE driver for Marvell Yukon chipset and SysKonnect Gigabit
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Ethernet adapters. Derived from Linux skge driver (v1.13), which was
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * based on earlier sk98lin, e100 and FreeBSD if_sk drivers.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * This driver intentionally does not support all the features of the
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * original driver such as link fail-over and link management because
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * those should be done at higher levels.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Modified for iPXE, July 2008 by Michael Decker <mrd999@gmail.com>
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Tested and Modified in December 2009 by
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Thomas Miletich <thomas.miletich@gmail.com>
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * This program is free software; you can redistribute it and/or modify
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * it under the terms of the GNU General Public License as published by
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * the Free Software Foundation; either version 2 of the License.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * This program is distributed in the hope that it will be useful,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * but WITHOUT ANY WARRANTY; without even the implied warranty of
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * GNU General Public License for more details.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * You should have received a copy of the GNU General Public License
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * along with this program; if not, write to the Free Software
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PCI_ROM(0x10b7, 0x80eb, "3C940B", "3COM 3C940", 0),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PCI_ROM(0x1186, 0x4C00, "DGE510T", "DLink DGE-510T", 0),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PCI_ROM(0x1186, 0x4b01, "DGE530T", "DLink DGE-530T", 0),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PCI_ROM(0x11ab, 0x4320, "id4320", "Marvell id4320", 0),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PCI_ROM(0x11ab, 0x5005, "id5005", "Marvell id5005", 0), /* Belkin */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PCI_ROM(0x1371, 0x434e, "Gigacard", "CNET Gigacard", 0),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PCI_ROM(0x1737, 0x1064, "EG1064", "Linksys EG1064", 0),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PCI_ROM(0x1737, 0xffff, "id_any", "Linksys [any]", 0)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void yukon_init(struct skge_hw *hw, int port);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void genesis_mac_init(struct skge_hw *hw, int port);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void genesis_link_up(struct skge_port *skge);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int skge_xmit_frame(struct net_device *dev, struct io_buffer *iob);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void skge_net_irq ( struct net_device *dev, int enable );
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic struct net_device_operations skge_operations = {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Avoid conditionals by using array */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Determine supported/advertised modes based on hardware.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic u32 skge_supported_modes(const struct skge_hw *hw)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Chip internal frequency for clock calculations */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Microseconds to chip HZ */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncenum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void skge_led(struct skge_port *skge, enum led_mode mode)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * I've left in these EEPROM and VPD functions, as someone may desire to
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * integrate them in the future. -mdeck
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * static int skge_get_eeprom_len(struct net_device *dev)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * struct skge_port *skge = netdev_priv(dev);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * u32 reg2;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * } while (!(offset & PCI_VPD_ADDR_F));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * return val;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * offset | PCI_VPD_ADDR_F);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * } while (offset & PCI_VPD_ADDR_F);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * u8 *data)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * struct skge_port *skge = netdev_priv(dev);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * struct pci_dev *pdev = skge->hw->pdev;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * int length = eeprom->len;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * u16 offset = eeprom->offset;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * if (!cap)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * return -EINVAL;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * eeprom->magic = SKGE_EEPROM_MAGIC;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * while (length > 0) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * u32 val = skge_vpd_read(pdev, cap, offset);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * int n = min_t(int, length, sizeof(val));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * memcpy(data, &val, n);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * length -= n;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * data += n;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * offset += n;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * return 0;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * u8 *data)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * struct skge_port *skge = netdev_priv(dev);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * struct pci_dev *pdev = skge->hw->pdev;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * int length = eeprom->len;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * u16 offset = eeprom->offset;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * if (!cap)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * return -EINVAL;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * if (eeprom->magic != SKGE_EEPROM_MAGIC)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * return -EINVAL;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * while (length > 0) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * int n = min_t(int, length, sizeof(val));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * if (n < sizeof(val))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * val = skge_vpd_read(pdev, cap, offset);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * memcpy(&val, data, n);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * skge_vpd_write(pdev, cap, offset, val);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * length -= n;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * data += n;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * offset += n;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * return 0;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Allocate ring elements and chain them together
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * One-to-one association of board descriptors with ring elements
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int i;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0, e = ring->start, d = vaddr; i < num; i++, e++, d++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Allocate and setup a new buffer for receiving */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void skge_rx_setup(struct skge_port *skge __unused,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync map = ( iob != NULL ) ? virt_to_bus(iob->data) : 0;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Resume receiving using existing skb,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Note: DMA address is not changed by chip.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * MTU not changed while receiver active.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Free all buffers in receive ring, assumes receiver stopped */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync DBG2(PFX "%s: Link is down.\n", skge->netdev->name);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void xm_link_down(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < PHY_RETRIES; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < PHY_RETRIES; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < PHY_RETRIES; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* set blink source counter */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* configure mac arbiter */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* configure mac arbiter timeout values */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* configure packet arbiter timeout */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void genesis_reset(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* reset the statistics module */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* disable Broadcom PHY IRQ */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Flush TX and RX fifo */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Convert mode to MII values */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* special defines for FIBER (88E1011S only) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Check status of Broadcom phy link */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void bcom_check_link(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* read twice because of latch */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Check Duplex mismatch */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* We are using IEEE 802.3z/D5.0 Table 37-4 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Phy on for 100 or 10Mbit operation
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int i;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* magic workaround patterns for Broadcom */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync static const struct {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* read Id from external PHY (all have the same address) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Optimize MDIO transfer by suppressing preamble. */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Workaround BCOM Errata for the C0 type.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Write magic patterns to reserved registers.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Workaround BCOM Errata for the A1 type.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Write magic patterns to reserved registers.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Workaround BCOM Errata (#10523) for all BCom PHYs.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Disable Power Management after reset.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Dummy read */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Workaround BCOM Errata #1 for the C5 type.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * 1000Base-T Link Acquisition Failure in Slave Mode
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Force to slave */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Set autonegotiation pause parameters */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Use link status change interrupt */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Restart Auto-negotiation */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Set DuplexMode in Config register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Do NOT enable Auto-negotiation here. This would hold
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * the link down because no IDLEs are transmitted
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Poll PHY for status changes */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* read twice because of latch */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Check Duplex mismatch */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* We are using IEEE 802.3z/D5.0 Table 37-4 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Enable PAUSE receive, disable PAUSE transmit */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Disable PAUSE receive, enable PAUSE transmit */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Poll to check for link coming up.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Since internal PHY is wired to a level triggered pin, can't
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * get an interrupt when carrier is detected, need to poll for
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * link coming up.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Verify that the link by checking GPIO register three times.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * This pin has the signal from the link_sync pin connected to it.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < 3; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Re-enable interrupt to detect link down */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void genesis_mac_init(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < 10; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Unreset the XMAC. */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Perform additional initialization for external PHYs,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * namely for the 1000baseTX cards that use the XMAC's
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * GMII mode.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Take external Phy out of reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Enable GMII interface */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Set Station Address */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* We don't use match addresses so clear */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Clear MIB counters */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Clear two times according to Errata #3 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* configure Rx High Water Mark (XM_RX_HI_WM) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* We don't need the FCS appended to the packet. */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * If in manual half duplex mode the other side might be in
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * full duplex mode, so ignore if a carrier extension is not seen
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * on frames received
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* We want short frames padded to 60 bytes. */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Enable the reception of all error frames. This is is
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * a necessary evil due to the design of the XMAC. The
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * XMAC's receive FIFO is only 8K in size, however jumbo
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * frames can be up to 9000 bytes in length. When bad
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * frame filtering is enabled, the XMAC's RX FIFO operates
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * in 'store and forward' mode. For this to work, the
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * entire frame has to fit into the FIFO, but that means
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * that jumbo frames larger than 8192 bytes will be
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * truncated. Disabling all bad frame filtering causes
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * the RX FIFO to operate in streaming mode, in which
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * case the XMAC will start transferring frames out of the
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * RX FIFO as soon as the FIFO threshold is reached.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * - Enable all bits excepting 'Octets Rx OK Low CntOv'
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * and 'Octets Rx OK Hi Cnt Ov'.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * - Enable all bits excepting 'Octets Tx OK Low CntOv'
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * and 'Octets Tx OK Hi Cnt Ov'.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Configure MAC arbiter */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* configure timeout values */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Configure Rx MAC FIFO */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Configure Tx MAC FIFO */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* enable timeout timers */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Disable Tx and Rx */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Clear Tx packet arbiter timeout IRQ */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Reset the MAC */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync } while (--retries > 0);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* For external PHYs there must be special handling */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (port == 0) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * enabling pause frame reception is required for 1000BT
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * because the XMAC is not reset if the link is going down
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Disable Pause Frame Reception */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Enable Pause Frame Reception */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Configure Pause Frame Generation
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Use internal and external Pause Frame Generation.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Sending pause frames is edge triggered.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Send a Pause frame with the maximum pause time if
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * internal oder external FIFO full condition occurs.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Send a zero pause time frame to re-start transmission.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* XM_PAUSE_DA = '010000C28001' (default) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* XM_MAC_PTIME = 0xffff (maximum) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* remember this value is defined in big endian (!) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * disable pause frame generation is required for 1000BT
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * because the XMAC is not reset if the link is going down
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Disable Pause Mode in Mode Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Turn on detection of Tx underrun */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* get MMU Command Reg. */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Workaround BCOM Errata (#10523) for all BCom Phys
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Enable Power Management after link up
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* enable Rx/Tx */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic inline void bcom_phy_intr(struct skge_port *skge)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Workaround BCom Errata:
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * enable and disable loopback mode if "NO HCD" occurs.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < PHY_RETRIES; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync DBG(PFX "%s: phy write timeout port %x reg %x val %x\n",
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < PHY_RETRIES; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync DBG(PFX "%s: phy read timeout port %x reg %x val %x\n",
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Marvell Phy Initialization */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void yukon_init(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct skge_port *skge = netdev_priv(hw->dev[port]);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Set Flow-control capabilities */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Restart Auto-negotiation */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* forced speed/duplex settings */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Enable phy interrupt on autonegotiation complete (or link up) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void yukon_reset(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void yukon_mac_init(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct skge_port *skge = netdev_priv(hw->dev[port]);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* WA code for COMA mode -- set PHY reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* hard reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* WA code for COMA mode -- clear PHY reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Set hardware config mode */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Clear GMC reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* disable Rx flow-control */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* enable Tx & Rx flow-control */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* MIB clear */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < GM_MIB_CNT_SIZE; i++)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* transmit control */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* receive control reg: unicast + multicast + no FCS */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* transmit flow control */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* transmit parameter */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* configure the Serial Mode Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* physical address: used for pause frames */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* virtual address for data */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* enable interrupt mask for counter overflows */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Initialize Mac Fifo */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Configure Rx MAC FIFO */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * because Pause Packet Truncation in GMAC is not working
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * we have to increase the Flush Threshold to 64 bytes
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * in order to flush pause packets in Rx FIFO on Yukon-1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Configure Tx MAC FIFO */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Go into power down mode */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void yukon_suspend(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* switch IEEE compatible power down mode on */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* set GPHY Control reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic u16 yukon_speed(const struct skge_hw *hw __unused, u16 aux)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Enable Transmit FIFO Underrun */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* enable Rx/Tx */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* restore Asymmetric Pause bit */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* We are using IEEE 802.3z/D5.0 Table 37-4 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* XXX restart autonegotiation? */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Set thresholds on receive queue's */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Enable store & forward on Tx queue's because
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Tx FIFO is only 4K on Genesis and 1K on Yukon
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Setup Bus Memory Interface */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void skge_qset(struct skge_port *skge, u16 q,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync const struct skge_element *e)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* optimization to reduce window on 32bit/33mhz */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge->mem = malloc_dma(RING_SIZE, SKGE_RING_ALIGN);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* FIXME: find out whether 64 bit iPXE will be loaded > 4GB */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if ((u64)skge->dma >> 32 != ((u64) skge->dma + RING_SIZE) >> 32) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync DBG(PFX "pci_alloc_consistent region crosses 4G boundary\n");
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma, NUM_RX_DESC);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* this call relies on e->iob and d->control to be 0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * This is assured by calling memset() on skge->mem and using zalloc()
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * for the skge_element structures.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync err = skge_ring_alloc(&skge->tx_ring, skge->mem + RX_RING_SIZE,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Initialize MAC */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Configure RAMbuffers - equally between ports and tx/rx */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync assert(!(skge->tx_ring.to_use != skge->tx_ring.to_clean));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Start receiver BMU */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* stop receiver */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void skge_rx_stop(struct skge_hw *hw, int port)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Stop transmitter */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Disable Force Sync bit and Enable Alloc bit */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Stop Interval Timer and Limit Counter of Tx Arbiter */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Reset PCI FIFO */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Reset the RAM Buffer async Tx queue */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic inline int skge_tx_avail(const struct skge_ring *ring)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync return ((ring->to_clean > ring->to_use) ? 0 : NUM_TX_DESC)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic int skge_xmit_frame(struct net_device *dev, struct io_buffer *iob)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Make sure all the descriptors written */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync dev->name, e - skge->tx_ring.start, (unsigned int)len);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Free all buffers in transmit ring */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic inline u16 phy_length(const struct skge_hw *hw, u32 status)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic inline int bad_phy_status(const struct skge_hw *hw, u32 status)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Free all buffers in Tx ring which are no longer owned by device */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (e = ring->to_clean; e != ring->to_use; e = e->next) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync u32 control = ((const struct skge_tx_desc *) e->desc)->control;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Can run lockless until we need to synchronize to restart queue. */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < NUM_RX_DESC; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* nothing to do here */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync DBG2("refilling rx desc %zd: ", (ring->to_clean - ring->start));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* We pass the descriptor to the NIC even if the
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * allocation failed. The card will stop as soon as it
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * encounters a descriptor with the OWN bit set to 0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * thus never getting to the next descriptor that might
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * contain a valid io_buffer. This would effectively
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * stall the receive.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync for (i = 0; i < NUM_RX_DESC; i++) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* catch RX errors */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* report receive errors */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* io_buffer passed to core, make sure we don't reuse it */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* reading this register ACKs interrupts */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Link event? */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* restart receiver */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic const struct {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic const char *skge_board_name(const struct skge_hw *hw)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int i;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Setup the board data structure, but don't bring up
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * the port(s)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* do a SW reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* clear PCI errors, if any */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* restore CLK_RUN bits (for Yukon-Lite) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* read the adapters RAM size */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* special case: 4 x 64k x 36, offset = 0x80000 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync else if (t8 == 0)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Use PHY IRQ for all but fiber based Genesis board */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* switch power to VCC (WA for VAUX problem) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* avoid boards with stuck Hardware error bits */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Clear PHY COMA */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* turn off hardware timer (unused) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* enable the Tx Arbiters */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Initialize ram interface */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Set interrupt moderation for Transmit only
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Receive interrupts avoided by NAPI
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Initialize network device */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic struct net_device *skge_devinit(struct skge_hw *hw, int port,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct net_device *dev = alloc_etherdev(sizeof(*skge));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Auto speed and flow control */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* read the mac address */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync memcpy(dev->hw_addr, (void *) (hw->regs + B2_MAC_1 + port*8), ETH_ALEN);
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync hw->regs = (unsigned long)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0),
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /* Failure to register second port need not be fatal */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Enable or disable IRQ masking.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * @v netdev Device to control.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * @v enable Zero to mask off IRQ, non-zero to enable IRQ.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * This is a iPXE Network Driver API function.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic void skge_net_irq ( struct net_device *dev, int enable ) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync .id_count = ( sizeof (skge_id_table) / sizeof (skge_id_table[0]) ),