Cross Reference: /vbox/src/VBox/VMM/VMMAll/EMAll.cpp

Lines Matching refs:val64
1769     uint64_t val64;
1770     int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1775         rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1777         rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1781         LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1851     uint64_t val64;
1855     int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1858         rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1860         rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2021                 valpar1 = param1.val.val64;
2025                 pParam1 = (RTGCPTR)param1.val.val64;
2044                 pParam2 = (RTGCPTR)param2.val.val64;
2055                 valpar2 = param2.val.val64;
2149                 pParam1 = (RTGCPTR)param1.val.val64;
2236                 pParam1 = (RTGCPTR)param1.val.val64;
2318                 pParam1 = (RTGCPTR)param1.val.val64;
2338                 valpar2 = param2.val.val64;
2416     RTGCUINTREG ValPar2 = param2.val.val64;
2421     RTGCPTR GCPtrPar1 = param1.val.val64;
2489                 pParam1 = (RTGCPTR)param1.val.val64;
2511                 valpar2 = param2.val.val64;
2583             pParam1 = (RTGCPTR)param1.val.val64;
2590                 valpar2 = param2.val.val64;
2658     uint64_t ValPar2 = param2.val.val64;
2661     RTGCPTR GCPtrPar1 = param1.val.val64;
2724         uint64_t val64;
2734             pDest = (RTGCPTR)param1.val.val64;
2746             val64 = param2.val.val64;
2755             LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2757             LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X  (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2762         rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2796         uint64_t val64;
2807             pSrc = (RTGCPTR)param2.val.val64;
2817         rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2827             case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg,  (uint8_t) val64); break;
2828             case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2829             case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2830             case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2843             LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2845             LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
3033         valpar = param2.val.val64;
3049         GCPtrPar1 = param1.val.val64;
3115         GCPtrPar1 = param1.val.val64;
3188                 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3271         addr = (RTGCPTR)param1.val.val64;
3390         pParam1 = (RTGCPTR)param1.val.val64;