Lines Matching refs:UINT32
345 UINT32 Bar[6]; // Base Address Registers
346 UINT32 CardBusCISPtr; // CardBus CIS Pointer
349 UINT32 ROMBar; // Expansion ROM Base Address
353 UINT32 Reserved1;
365 UINT32 Bar[2]; // Base Address Registers
377 UINT32 PrefetchableBaseUpper; // Pre-fetchable Base Upper 32 bits
378 UINT32 PrefetchableLimitUpper; // Pre-fetchable Limit Upper 32 bits
384 UINT32 ROMBar; // Expansion ROM Base Address
394 UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
404 UINT32 MemoryBase0; // Memory Base Register 0
405 UINT32 MemoryLimit0; // Memory Limit Register 0
406 UINT32 MemoryBase1;
407 UINT32 MemoryLimit1;
408 UINT32 IoBase0;
409 UINT32 IoLimit0; // I/O Base Register 0
410 UINT32 IoBase1; // I/O Limit Register 0
411 UINT32 IoLimit1;
424 UINT32 LegacyBase; // Optional 16-Bit PC Card Legacy
427 UINT32 Data[46];
439 UINT32 Data[48];
446 UINT32 PcieDeviceCap;
449 UINT32 LinkCap;
452 UINT32 SlotCap;
457 UINT32 RootStatus;