Lines Matching refs:rps
667 rps.work);
671 spin_lock_irq(&dev_priv->rps.lock);
672 pm_iir = dev_priv->rps.pm_iir;
673 dev_priv->rps.pm_iir = 0;
676 spin_unlock_irq(&dev_priv->rps.lock);
681 mutex_lock(&dev_priv->rps.hw_lock);
684 new_delay = dev_priv->rps.cur_delay + 1;
691 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
692 new_delay = dev_priv->rps.rpe_delay;
694 new_delay = dev_priv->rps.cur_delay - 1;
699 if (new_delay >= dev_priv->rps.min_delay &&
700 new_delay <= dev_priv->rps.max_delay) {
707 mutex_unlock(&dev_priv->rps.hw_lock);
809 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
812 * The mask bit in IMR is cleared by dev_priv->rps.work.
815 spin_lock_irqsave(&dev_priv->rps.lock, flags);
816 dev_priv->rps.pm_iir |= pm_iir;
817 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
819 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
821 queue_work(dev_priv->wq, &dev_priv->rps.work);
893 spin_lock_irqsave(&dev_priv->rps.lock, flags);
894 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
895 if (dev_priv->rps.pm_iir) {
896 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
900 queue_work(dev_priv->wq, &dev_priv->rps.work);
902 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
2778 /* Our enable/disable rps functions may touch these registers so
3558 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);